Abstract: Triangular wave oscillation circuits generate A-wave and B-wave with phases opposite to each other, and are capable of independently controlling oscillation levels of the A-wave and the B-wave. A slope switching circuit including an output voltage monitoring circuit, a slope switching control circuit, and an inverter, monitors output voltages of the triangular wave oscillation circuits, to switch an output voltage generation mode of one triangular wave oscillation circuit whose triangular wave reaches a high level, from an up-slope waveform mode to a down-slope waveform mode, and to switch an output voltage generation mode of the other triangular wave oscillation circuit, from the down-slope waveform mode to the up-slope waveform mode. An oscillation level control circuit controls an oscillation level of the other triangular wave oscillation circuit so that the output voltage of the other of the triangular wave oscillation circuit becomes a reference lower limit crest value during the switching.

Abstract: In an amplifier including first and second power supply terminals, first and second output terminals, a first load connected between the first power supply terminal and the first output terminal, a second load connected between the first power supply terminal and the second output terminal, a constant current source connected to the second power supply terminal, a first transistor connected between the first output terminal and the constant current source, a control terminal of the first transistor being adapted to receive an input voltage, and a second transistor connected between the second output terminal and the constant current source, a control terminal of the second transistor being adapted to receive a reference voltage, an amplification and output impedance switching circuit is connected between the first and second output terminals, so that the amplifier and output impedance switching circuit controls an amplification and output impedance of the amplifier in accordance with a control signal.

Abstract: A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is precharged. A state in a simultaneous access operation is reproduced by activating the word line WLB during a time period of activating the word line WLA regardless of a delay difference of the clock signal and maintaining Vds of an access transistor of A port at a constant value.

Abstract: In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

Abstract: In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Abstract: A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.

Abstract: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

Abstract: A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression.

Abstract: A low amplitude differential output circuit includes a pre-buffer circuit configured to output a main buffer drive signal of a-first drive signal and a second drive signal which are complimentary signals, as a differential signal; and a main buffer circuit connected with the pre-buffer circuit to output a differential output signal in response to the main buffer drive signal. Each of the first drive signal and the second drive signal has an amplitude between a first voltage and a second voltage, and the first drive signal and the second drive signal take a same voltage between the first voltage and a middle voltage between the first voltage and the second voltage.

Abstract: Boosting operation of a charge pump is performed at a fixed period irrespective of the state of a load.

Abstract: A controller driver includes an overdrive processing unit generating corrected image data based on image data and image data of one frame previous to the image data, a data line driver generating a liquid crystal driving voltage, a roundabout route bypassing the overdrive processing unit and allowing the one frame previous image data to be input to the data line driver, a second expander outputting the one frame previous image data to one of a connection route to the overdrive processing unit and the roundabout route, a command controller supplying a moving/still image switching signal S1 for indicating switching between moving image display and still image display to the second expander. The second expander selects the connection route to the overdrive processing unit in displaying a moving image and selects the roundabout route in displaying a still image.

Abstract: A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a manner that the MISR is caused to operate at a high-speed clock when the compressed data is generated and stored, and at a low-speed clock when the stored compressed data is read out and output.

Abstract: A Controller Area Network (CAN) node includes a conversion and retransmission unit which retransmits a transmit message if the transmit message carries a retransmission ID out of ID codes, by changing the ID code of the transmit message to a retransmission-specific ID corresponding to the retransmission ID, where the ID codes indicate priorities of transmit messages, the retransmission ID indicates that the transmit message is to be retransmitted, and the retransmission-specific ID is an ID code specifically for use in retransmission, and a conversion and reception unit which checks whether an original message corresponding to a retransmit message has been received successfully, the retransmit message being a receive message carrying the retransmission-specific ID, and discards the retransmit message if the original message corresponding to the retransmit message has been received successfully, but converts the ID code of the retransmit message into a retransmission ID corresponding to the retransmission-spec

Abstract: An exemplary aspect of the present invention is a data processing apparatus for processing a loop in a pipeline that includes an instruction memory and a fetch circuit that fetches an instruction stored in the instruction memory. The fetch circuit includes an instruction queue that stores an instruction to be output from the fetch circuit, an evacuation queue that stores an instruction fetched from the instruction memory, a selector that selects one of the instruction output from the instruction queue and the instruction output from the evacuation queue, and a loop queue that stores the instruction selected by the selector and outputs to the instruction queue.

Abstract: A simple circuit that supports high and low data rates is provided. The circuit includes: a detection circuit 11 for detecting whether D1?D2 or D1?D3, assuming that logical values of an input data signal DATAIN sampled at timings t1, t2, and t3 (t2<t1<t3) of edges of clock signals CLK0 and CLK1 are D1, D2, and D3, respectively; and a clock generation circuit 14 for changing phases of the clock signals CLK0 and CLK1 based on detection results from the detection circuit 11, so that timings at which the logical values of the input data signal DATAIN change correspond to the timings t2 and t3.

Abstract: In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell.

Abstract: A semiconductor integrated circuit includes an oscillation circuit for generating multiple clocks of mutually different phases, and is also characterized in selecting a single clock FCLK_P from among multiple clocks FCLK_P [n-1:0] for use in transmitting IQ Serial transmission signals and, utilizing the FCLK_P to transmit an IQ Serial transmission signal.

Abstract: A method of manufacturing a semiconductor apparatus including a process of applying viscous liquid. The method applies viscous liquid onto a principal surface of a substrate, coats the viscous liquid closely with flexible coating material having a higher bonding strength with molecules of the viscous liquid than an intermolecular bonding strength of molecules of the viscous liquid, and then strips away the coating material together with part of the viscous liquid.

Abstract: An object of the invention is to provide a semiconductor device which includes a barrier metal having high adhesiveness and diffusion barrier properties and a method of manufacturing the semiconductor device. The invention provides a semiconductor device manufacturing method including forming a first layer made of a material containing silicon on a base substance; forming a second layer containing metal and nitrogen on the first layer; and exposing the second layer to active species obtained from plasma in an atmosphere including reducing gas.

Abstract: A drive circuit for driving a display device includes: a first data latch circuit that holds image data corresponding to one line from; a second data latch circuit that holds image data held in the first data latch circuit; a decoding circuit that decodes the image data held in the second data latch circuit; a gradation amplifier circuit that includes gradation amplifiers that amplify or buffer, and output respective gradation voltages; a gradation voltage selection circuit that selects gradation voltages necessary for display; a decision circuit that decides on use/non-use of gradations, using the image data; and an enabling/disabling circuit that selectively disables operation of the gradation amplifiers corresponding to gradations that are identified as not to be used, using the decision results output from the decision circuit.