Patents Assigned to NEC Electronics
  • Patent number: 7737481
    Abstract: A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d2 (first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d3 (second pitch) representing a pitch of portions provided with the bit contacts, and distance d4 between two such bit lines in the portions provided with the bit contacts is larger than width d5 of the bit lines in the portions provided with the bit contacts.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Sakoh, Mami Toda
  • Patent number: 7737555
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
  • Patent number: 7737558
    Abstract: Provided is a semiconductor device having a high-frequency interconnect, first dummy conductor patterns, an interconnect, and second dummy conductor patterns. The first dummy conductor patterns are arranged in the vicinity of the high-frequency interconnect, and the second dummy conductor patterns are arranged in the vicinity of the interconnect. The minimum value of distance between the high-frequency interconnect and the first dummy conductor patterns is larger than the minimum value of distance between the interconnect and the second dummy conductor patterns.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yasutaka Nakashiba
  • Publication number: 20100144154
    Abstract: Aimed at suppressing roughening in a circumferential portion of a layer to be etched in the process of removing a hard mask formed thereon, an etching apparatus of the present invention has a process chamber, an electrode, a stage, and a shadow ring, wherein the process chamber allows an etching gas to be introduced therein; the electrode is disposed in the process chamber, and is used for generating plasma by ionizing the etching gas; the stage is disposed in the process chamber, onto which a substrate is disposed; the shadow ring has an irregular pattern on the inner circumferential edge thereof, and is disposed in the process chamber and placed above the stage 30, so as to cover a circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner.
    Type: Application
    Filed: April 21, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Masahiro Komuro
  • Publication number: 20100145614
    Abstract: A map drawing device can reduce the use amount of a video memory and power consumption. The map drawing device comprises an arithmetic processing unit that operates according to a map drawing program and outputs an address of map data to be drawn; an address difference detection circuit that makes comparison of each address of map data output one by one from the arithmetic processing unit and determines whether or not to output a transfer start trigger signal to a data transfer control unit; and a data transfer control unit that directly transfers the map data with the address instructed by the arithmetic processing unit from a map data storage medium to the video memory based on the transfer start trigger signal output from the address difference detection circuit.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Yasuhiro KOIDO
  • Publication number: 20100140740
    Abstract: A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Koujirou Matsui
  • Publication number: 20100144091
    Abstract: A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Masaya Kawano, Koji Soejima, Nobuaki Takahashi, Yoichiro Kurita, Masahiro Komuro, Satoshi Matsui
  • Publication number: 20100140672
    Abstract: A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between the stopper layer and the cap layer. The cap layer includes a high concentration cap layer, and a low concentration cap layer provided directly or indirectly under the high concentration cap layer and having an impurity concentration lower than the high concentration cap layer.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Masayuki AOIKE, Yasunori Bito
  • Publication number: 20100142169
    Abstract: The electronic device, which allows inhibiting the breaking-away of the element from the frame member, even if the temperature change of the electronic device is repeated, and the process for manufacturing the electronic device, are achieved. An electronic device includes a photo-sensitive element formed in a wafer, a frame member installed on the wafer to surround a functional unit, and an encapsulating resin layer filling a circumference of the frame member.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Kenji UCHIDA, Koki Hirasawa
  • Publication number: 20100140616
    Abstract: Disclosed herewith is an electronic device capable of preventing the surfaces of the analyzing terminals from such external factors as oxidation, etc. so as to improve the accuracy of the analysis of the electronic device. The electronic device has plural signal lines and is to be mounted on a wiring substrate. The electronic device also includes plural lead terminals connected to the signal lines electrically and to be mounted on the wiring substrate, as well as analyzing terminals connected electrically to the signal lines and to be connected to an analyzing device upon analyzing the electronic device respectively and a protective member with insulating performance, which covers at least one of the analyzing terminals 1 and can be removed upon analyzing. The protective member is made of, for example, resin and it is removed when the electronic device is to be analyzed.
    Type: Application
    Filed: April 28, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Daiki Kaya
  • Publication number: 20100139963
    Abstract: Embodiments of the invention provide an interconnect substrate capable of improving the connection reliability and yield of a semiconductor device, a method of manufacturing the interconnect substrate, and a semiconductor device using the interconnect substrate. An interconnect substrate according to an embodiment of the invention includes: a substrate; an electrode pad formed over the substrate; an insulating film (solder resist film) formed over the substrate; an opening formed in the insulating film, in which the upper surface of the electrode pad is exposed on the bottom surface of the opening; and a metal film formed over the upper surface of the electrode pad and side surface of the insulating film in the opening. At least a portion of the edge of an upper surface of the metal film is higher than the other portions of the upper surface of the metal film.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kiminori Ishido
  • Publication number: 20100140677
    Abstract: A semiconductor device of the present invention has a first contact and a second contact which are located over a device isolation film so as to be opposed with each other, and have a length in the horizontal direction larger than the height; a first electro-conductive pattern located on the first contact and is formed in at least a single interconnect layer; a second electro-conductive pattern located on the second contact so as to be opposed with the first electro-conductive pattern; and an interconnect formed in an upper interconnect layer which is located above the first electro-conductive pattern and the second electro-conductive pattern, so as to be located in a region above the first electro-conductive pattern and the second electro-conductive pattern.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Masayuki FURUMIYA, Yasutaka NAKASHIBA
  • Publication number: 20100142606
    Abstract: A transmission line loss compensation circuit and transmission line loss compensation method is provided. The transmission line loss compensation circuit includes a linear equalizer that compensates for a transmission line loss of high frequency components, a high-pass filter that extracts high frequency components from an output of the linear equalizer, a peak detector that compares the peak voltage of a high-pass filter output to first and second reference voltages, and a control circuit that controls the compensation intensity of the linear equalizer based on the detection results of the peak detector so that the peak voltage becomes an intermediate voltage between the first reference voltage and the second reference voltage.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Hiromu Kato
  • Patent number: 7732790
    Abstract: An ion implanting apparatus is provided, which prevents a failure of the processing object caused by a scattering of the deposited particles of the ion species on an inner surface of a through hole of a member that forms a beam geometry of an ion beam. Since at least an inner surface of the through hole 222 of the member 220 having a through hole and being capable of forming a beam geometry is coated with a thermal spraying film, unwanted deposition of the ion species on the inner surface of the through hole 222 is inhibited. Moreover, since a deposition film generated on the surface of the thermal spraying film has an unoriented poly-crystalline structure that exhibits extremely higher inter-layer adhesiveness, a failure of the processing object caused by a scattering of the particles peeled-off from the deposition layer is prevented.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Jitsuo Takada, Minoru Ikeda, Satoshi Matsufune
  • Patent number: 7733120
    Abstract: Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment control signal holding circuit and a monitor circuit. The replica resistor control counter counts up and down based on the comparison result by the comparator to output a control signal to the replica resistor. The resistor-under-adjustment control signal holding circuit holds a control signal that is delivered to the terminal resistor.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiromu Kato, Masahiro Takeuchi
  • Patent number: 7732895
    Abstract: In a semiconductor device, a plurality of triple-stacked structures all having the same structure are provided. Each of the triple-stacked structures includes one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takeshi Toda
  • Patent number: 7734001
    Abstract: A fractional frequency divider circuit with a small circuit scale that outputs a clock with a duty ratio of 50%, and a data transmission apparatus comprising same. The fractional frequency divider circuit is constituted by multiple master-slave flip-flops, and comprises an integer frequency divider circuit that frequency-divides a clock signal with a frequency-division ratio of 1/N(N is an integer), and a logic circuit into which multiple signals outputted from master stages and slave stages of the master-slave flip-flops are inputted and that outputs a signal with a duty ratio of 50% obtained by frequency-dividing the clock signal with a frequency-division ratio of 2/N. The data transmission apparatus is constituted such that it is possible to switch over between a frequency-multiplied clock outputted by a PLL and a clock obtained by frequency-dividing the frequency-multiplied clock with the fractional frequency divider circuit for each channel.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takanori Saeki
  • Patent number: 7733164
    Abstract: In a semiconductor device, a monitoring circuit monitors and detects a quantity of noise in the semiconductor device. A control circuit has capacitances and controls connections to the capacitances such a decoupling capacitance value provided between a first power supply and a second power supply is dynamically adjusted based on the detected noise quantity.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Umamichi, Katsunori Shirai
  • Patent number: 7733192
    Abstract: According to one aspect of the present invention, there is provided a voltage controlled oscillator controlling frequency of an output signal according to input voltage, the voltage controlled oscillator including a current controlled oscillator setting the frequency of the output signal based on control current, and a voltage-current converter including a transistor controlling a current amount of the control current according to the input voltage, in which the voltage-current converter is supplied with control voltage, and threshold value voltage of the transistor is controlled according to the control voltage.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Ryota Yamamoto
  • Patent number: 7733728
    Abstract: Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical direction, common sources CS that extend in a horizontal direction below the select gates SG outside a cell region, word lines W0 to W15 that extend above the select gates SG in the horizontal direction within the cell region, a plurality of storage nodes disposed in the vicinity of intersecting portions between the word lines W0 to W15 and the select gates SG, respectively, below the word lines W0 to W15, and a bit line MGB for transmitting to a sense amplifier 11 information on one of the storage nodes through a selection switch 21. In the main cell division unit 20a, an inversion layer is formed below each of the select gates SG within the cell region by applying a positive voltage to each of the select gates SG.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 8, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naoaki Sudo