Patents Assigned to NEC Electronics
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Patent number: 7733154Abstract: A semiconductor device includes a level shift circuit to convert an input signal having an amplitude from a first power supply potential to a second power supply potential to a signal having an amplitude from the first power supply potential to a third power supply potential, a first output portion to output voltage generated from the third power supply potential to an output terminal based on the output of the level shift circuit, the first output portion including a NMOS transistor, and a second output portion to output voltage generated from the third power supply potential to an output terminal based on the output of the level shift circuit, the second output portion including a PMOS transistor.Type: GrantFiled: June 9, 2008Date of Patent: June 8, 2010Assignee: NEC Electronics CorporationInventor: Shougo Kawahigashi
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Patent number: 7732896Abstract: A semiconductor apparatus comprises a plurality of transistor devices including a control terminal being inputted with a control signal and a first and a second terminals that a current flows therein according to the control signal, and a plurality of substrate conductive portions each formed in a region different from a region where the plurality of transistor devices are formed therein, wherein the transistor devices are connected to the substrate conductive portions, and each of the substrate conductive portion includes a semiconductor layer separated from other substrate conductive portions.Type: GrantFiled: July 5, 2006Date of Patent: June 8, 2010Assignee: NEC Electronics CorporationInventor: Kouzi Hayasi
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Patent number: 7733079Abstract: A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.Type: GrantFiled: September 25, 2007Date of Patent: June 8, 2010Assignee: NEC Electronics CofrporationInventor: Hidemi Nakashima
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Patent number: 7733133Abstract: A power switch circuit includes an output transistor which is connected between a first power supply terminal and an output terminal, and drives a load, an abnormality detecting circuit which detects an abnormal state of the output transistor, a resistance element which generates a resistance component by a diffusion layer formed on a well region, and is provided between an input terminal and a control terminal of the output transistor, and a well potential switching circuit which switches a voltage to be supplied to the well region between a voltage of the output terminal and a voltage of a second power supply terminal based on a detection result by the abnormality detecting circuit.Type: GrantFiled: December 15, 2008Date of Patent: June 8, 2010Assignee: NEC Electronics CorporationInventors: Hiroshi Yanagigawa, Masaki Kojima
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Publication number: 20100134229Abstract: A transmission-line transformer which includes a core composed of a magnetic substance, and a transmission line, wherein the core includes a body having the transmission line wound therearound, and a movable unit which can move relative to the body in keeping contact therewith, wherein the transmission-line transformer is provided on a substrate, at least a portion of the movable unit (a head, for example) is located on the opposite side of the substrate, while placing the body in between, and the movable unit is moved relative to the body, by an operation effected to at least the portion (the head, for example).Type: ApplicationFiled: December 1, 2009Publication date: June 3, 2010Applicant: NEC Electronics CorporationInventor: Takekatsu UEKI
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Patent number: 7728358Abstract: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed.Type: GrantFiled: August 7, 2008Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventors: Masataka Ono, Akiko Fujita
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Patent number: 7729383Abstract: A multiplexer according to an embodiment of the present invention multiplexes a video ES and an audio ES to generate a transport stream TS, and includes a video buffer, an audio buffer, and a multiplexing unit. A multiplexing unit executes simulation of a buffer occupation necessary for a video ES upon decoding the TS, and controls multiplexing of the video ES not to cause overflow of a buffer based on the simulation result. In the simulation, a predetermined time ?t is divided by N ((main buffer leak rate/system clock frequency)×N (N is an integer)=integer), the remainder R is carried over to the next calculation, and a current main buffer leak data amount is calculated by integer arithmetic based on the integral quotient.Type: GrantFiled: April 9, 2007Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Yoshikazu Aoki
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Patent number: 7728432Abstract: A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the insulating film. The copper interconnection includes: a first copper interconnection having a relatively narrow width; and a second copper interconnection having a relatively wide width. The first copper interconnection has the top surface thereof principally composed of copper, and the second copper interconnection has the top surface thereof principally composed of copper.Type: GrantFiled: July 21, 2005Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Hiroyuki Kunishima
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Patent number: 7728440Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.Type: GrantFiled: January 23, 2004Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Hirokazu Honda
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Patent number: 7728444Abstract: A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points. Each of the plurality of semiconductor chips includes first and second terminals. Moreover, a first wiring up to the first terminals and a second wiring up to the second terminals are in a positional relationship of being shifted parallel to each other in a planar direction of the wiring board so as not to come into electrical contact with each other.Type: GrantFiled: January 9, 2008Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Akimori Hayashi
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Patent number: 7728407Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.Type: GrantFiled: May 16, 2007Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Takehiro Ueda
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Patent number: 7727831Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.Type: GrantFiled: September 20, 2005Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Kinya Ohtani
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Patent number: 7728434Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.Type: GrantFiled: December 21, 2007Date of Patent: June 1, 2010Assignee: NEC Electronics CorporationInventor: Akira Furuya
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Publication number: 20100127260Abstract: To improve a transmission rate of an antireflection film, the antireflection film includes: a first silicon oxide film (2), which is formed on a silicon substrate (1); a polysilicon film (3), which is formed on the first silicon oxide film (2) to a thickness of 6 nm through 14 nm; and a second silicon oxide film (4), which is formed on the polysilicon film (3). The transmission rate of the antireflection film is further improved if a thickness of the first silicon oxide film (2) is set to 14 nm through 35 nm. When used in a photoelectric conversion element for such as a solid state image sensor and a photovoltaic generator, the antireflection film may enhance efficiency of photoelectric conversion.Type: ApplicationFiled: November 18, 2009Publication date: May 27, 2010Applicant: NEC Electronics CorporationInventor: Eiji Matsuyama
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Publication number: 20100127357Abstract: A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference side the dummy interconnect is formed on, the more upper layer the dummy interconnect is arranged on.Type: ApplicationFiled: December 19, 2008Publication date: May 27, 2010Applicant: NEC Electronic CorporationInventor: Hokuto Kumagai
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Publication number: 20100127733Abstract: Provided is a duty detection circuit including: a first capacitor; a first transistor that controls charge or discharge currents of the first capacitor during a first period of a clock signal; a second capacitor; a second transistor that controls charge or discharge currents of the second capacitor during a second period of the clock signal; and a latch circuit that detects that a potential of one of the first capacitor and the second capacitor reaches a predetermined potential, and latches an output based on a result of the detection.Type: ApplicationFiled: November 23, 2009Publication date: May 27, 2010Applicant: NEC Electronics CorporationInventor: Kazutaka KIKUCHI
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Patent number: 7724070Abstract: A charge charge-pump circuit according to an embodiment of the invention includes: a first boosting capacitor; a second boosting capacitor series-connected with the first boosting capacitor; a first boosting clock driver connected between the first boosting capacitor and the second boosting capacitor and boosting the first boosting capacitor; and a second boosting clock driver connected with the second boosting capacitor and boosting the first boosting capacitor and the second boosting capacitor after the first boosting clock driver boosts the first boosting capacitor.Type: GrantFiled: December 16, 2005Date of Patent: May 25, 2010Assignee: NEC Electronics CorporationInventor: Ikuo Fukami
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Patent number: 7723848Abstract: A silica residue is generated, due to a presence of a step formed by a presence of the first layer metallic interconnect, and then, the residual silica is etched to form hollow portions when vias for the metallic interconnect provided in a layer above thereof is formed, and further, insulating materials remained above the hollow portions flakes off to create contaminants, leading to a reduction in the production yield. In the present invention, interconnects provided in a layer underlying a via group, which are provided for coupling to the upper layer interconnect layer, are disposed so as to cover vias composing its via group.Type: GrantFiled: September 18, 2006Date of Patent: May 25, 2010Assignee: NEC Electronics CorporationInventor: Hiroki Matsumoto
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Patent number: 7724107Abstract: A phase shifter includes a first signal path in which a first unit is disposed to advance a phase of a signal; a second signal path in which a second unit with no shunt capacitor is disposed to change the phase of the signal such that the changed phase is delayed than the advanced phase by the first unit; and a switch section configured to switch between the first signal path and said second signal path. The first unit comprises a filter, and the second unit is a transmission line.Type: GrantFiled: January 17, 2008Date of Patent: May 25, 2010Assignee: NEC Electronics CorporationInventor: Tatsuya Miya
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Patent number: 7723837Abstract: A technology providing an improvement in the durability in the condition of changing the temperature, while ensuring characteristics such as the applicability to applications utilizing larger electric current, lower resistance and the like can be achieved. A semiconductor device 100 includes a ceramic multiple-layered interconnect substrate 120, a silicon chip 110 that is flip-bonded to a chip-carrying region of the ceramic multiple-layered interconnect substrate 120, and an external connecting bumps 161 and an external connecting bumps 163, which are provided in the side that the silicon chip 110 of the ceramic multiple-layered interconnect substrate 120 is carried. The silicon chip 110 includes a front surface electrode and a back surface electrode.Type: GrantFiled: January 19, 2006Date of Patent: May 25, 2010Assignee: NEC Electronics CorporationInventors: Takekazu Tanaka, Ikuo Komatsu
