Abstract: The dicing machine includes a rotary blade with a rotating shaft, applicable to processing a work, and a disk-shaped presser rotatably supported by the rotating shaft on a side of the blade, so as to roll on an upper face of the work independently from the blade.

Abstract: A semiconductor laser has a semiconductor substrate, a lower cladding layer formed on the semiconductor substrate, an active layer disposed above the lower cladding layer, a first upper cladding layer disposed above the active layer, a second upper cladding layer disposed above the first upper cladding layer and having a mesa structure, a high-order mode filter layer formed on both side faces of the second upper cladding layer, continuously extending from the both side faces onto at least a part of a side region on both sides of the second upper cladding layer and having a band gap not exceeding a band gap of the active layer, and a block layer formed on the high-order mode filter layer and on a side region on both sides of the second upper cladding layer and including a layer having a band gap greater than a band gap of the active layer.

Abstract: Provided is a semiconductor device which includes, on the same semiconductor substrate, a first FET and a second FET higher in threshold voltage than the first FET. The first FET includes a first gate insulating film and a first gate electrode. The second FET includes a second gate insulating film and a second gate electrode. The first gate electrode, the second gate insulating film, and the second gate electrode contain at least one metal element selected from the group consisting of Hf, Zr, Al, La, Pr, Y, Ta, and W. Concentration of the at least one metal element at an interface between the second gate insulating film and the second gate electrode in the second FET is higher than concentration of the at least one metal element at an interface between the first gate insulating film and the first gate electrode in the first FET.

Abstract: In a liquid crystal display driving circuit, upon time-sharing output of gray scale voltages from an amplifier of an output circuit for each unit pixel composed of three sub-pixels of red (R), green (G) and blue (B) in the output sequence of R, G and B, a data matching detector compares gray scale data corresponding to R, G and B sub-pixels for each unit pixel and, it they match in all pixels of each scan line, a driving time of the amplifier is set such that G output interval and B output interval are shorter than R output interval at the top by an output control signal AS output from a control signal generator.

Abstract: A phase shifter selectively switches between a low-pass filter 13 and a high-pass filter 12 using single pole double throw switches 10a and 10b provided on the input and output sides, respectively, and operatively linked to each other. The single pole double throw switches 10a and 10b include FETs Q1c and Q1d that connect single pole side junctions and the low-pass filter, respectively, and inductance circuits (L1c and R2c, and L1d and R2d) connected in parallel with FETs Q1c and Q1d, respectively. The inductance circuits are respectively comprised of the inductor L1c and the resistor R2c connected in series and of the inductor L1 d and the resistor R2d connected in series.

Abstract: Disclosed is a variable gain circuit, which operates in a region where the gain varies substantially exponentially with respect to a control voltage, having an operation region in which the gain varies substantially with an exponential function {(?{square root over (1?x)}??{square root over (2)})2+K}/{(?{square root over (1+x)}??{square root over (2)})2+K} where 0?K?1 and x is a variable corresponding to the control voltage. The denominator and the numerator of the above function are given by a first sum current and a second sum current, respectively. The first sum current is a sum of the drain current of a first transistor and a constant current, and the second sum current is a sum of the drain current of a second transistor and the constant current. The first and second transistors have sources grounded, having gates connected common and supplied with a bias voltage, and having back-gates supplied with control voltages differentially.

Abstract: In related arts, a body voltage needs to be controlled by separately detecting external environment such as temperature. In the related art, variation such as a process parameter for each individual product has not been considered. A semiconductor integrated circuit according to the present invention includes a comparator comparing a leak current of a first conductive type transistor with a leak current of a second conductive type transistor to output a comparing result, and a conduction control signal generator outputting a signal determining a conduction state of the first conductive type transistor and a conduction state of the second conductive type transistor in a power saving control target circuit in a power saving mode based on the comparing result.

Abstract: A semiconductor device for an IC tag comprises a receive unit for demodulating receive data from a received RF signal and a signal processing unit for detecting a command comprising data signals from the receive data demodulated by the receive unit and executing processing based on the command, wherein the signal processing unit has a command acceptance mode for detecting the command from the receive data and a command execution mode for executing the command, and cancels the data signal when the data signal is detected from the receive data in the command execution mode.

Abstract: A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

Abstract: A semiconductor device includes a differential circuit for receiving a differential signal at an input terminal and a detection circuit for outputting a detection signal when a predetermined signal is inputted to the input terminal. The detection circuit detects whether the differential signal becomes outside an electric input standard and outputs the detection signal.

Abstract: A charge coupled device is provided with: an output gate; a main CCD region operated in response to a set of clock signals; and an output region positioned between the output gate and the main CCD region and designed to transfer electric charges received from the main CCD region to the output gate. The main CCD region includes first and second transfer electrodes. The output region includes third and fourth transfer electrodes receiving clock signals which are phase-reversed from each other. The set of clock signals received by the main CCD region and the clock signals received by the output region are outputted from different driver circuits.

Abstract: A semiconductor device in which surge breakdown of interlayer-insulating film does not occur even when effectively suppressing variations in etching and proximity effects. The semiconductor comprises dummy patterns 7b that are made from a gate layer and shaped to be disposed within the surface shape of the insulating material of element-isolation areas 3a and are located on the insulating material of the element-isolation areas 3a; wherein dummy patterns 7b are located on an underlayer that includes area directly under wiring layers 10a that are located on layers above the gate layer.

Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.

Abstract: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter, polycrystalline silicon layer 56 and high dielectric constant insulating film 54 are selectively removed in stages by a dry etching through a mask of the resist layer 58, and subsequently, the residual portion of the high dielectric constant insulating film 54 and the silicon oxide film 52 are selectively removed by wet etching through a mask of polycrystalline silicon layer 56. A liquid mixture of phosphoric acid and sulfuric acid is employed for the etchant solution. The temperature of the etchant solution is preferably equal to or lower than 200 degree C., and more preferably equal to or less than 180 degree C.

Abstract: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.

Abstract: The semiconductor memory device includes a plurality of memory cell arrays and a control circuit that outputs a first signal and a second signal. The first signal instructs start of precharging of each memory cell array. The second signal instructs completion of the precharging and transition to a read access. The first signal is wired through one or more delay circuits to arrive at each memory cell array with a time difference, and the second signal is wired not through the one or more delay circuits.

Abstract: In a method of programming a differential programming semiconductor device, first identification data corresponding to first program data is outputted from an ID register of a program circuit in the device to a host. The first program data is programmed in a plurality of interconnections. The first program data is read from a storage unit based on the first identification data. Write data is generated based on the first program data and a second program data, which is to be newly programmed in the plurality of interconnections. The write data is transferred from the host to the device. The write data is written in the plurality of interconnections by the program circuit so as to program the second program data in the plurality of interconnections.

Abstract: An input signal detecting circuit includes a plurality of comparators configured to output a plurality of differential output signals in response to a differential input signal, respectively; and a differential exclusive OR circuit configured to output an exclusive OR resultant signal from the plurality of differential output signals outputted from the plurality of comparators. In at least one of the plurality of comparators, a DC operation voltage is changed in response to a control signal supplied to the comparator.