Abstract: A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying feedback control to an integrator adaptively and moment to moment, thereby raising the tracking speed of the recovered clock and improving the jitter tolerance characteristic.

Abstract: A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that is larger than that for the first pad, and the second testing-dedicated pad being in the second surface; coupling a wafer with a apparatus, and inspecting the wafer with a probe card, the wafer having a LSI, which is an object of an inspection, the apparatus applicable signal to the LSI formed in the wafer, and measurable electrical characteristics of the LSI formed in the wafer, and the probe card having one of the two substrates; dicing the wafer into semiconductor elements containing the LSI; and packaging the semiconductor element over the other of the two substrates.

Abstract: A light receiving circuit according to the present invention includes a current control voltage generation circuit 10 outputting control voltages Vcont1 and Vcont2, a first current adjusting circuit 11 generating a first output current Io1 by regulating a first input current Ii1 depending on a voltage difference of the control voltages Vcont1 and Vcont2, the first input current Ii1 generated by adding a first reference current Ia1 and an input current Ipd, a second current adjusting circuit 12 generating a second output current Io2 by regulating a second reference current Ia2 depending on the voltage difference of the control voltages Vcont1 and Vcont2, and a current voltage conversion circuit 13 generating a first output voltage Vo1 by converting the first output current Io1 to voltage based on a first resistance Rf1 and generating a second output voltage Vo2 by converting the second output current Io2 to voltage based on a second resistance Rf2.

Abstract: A semiconductor integrated circuit includes a target circuit with at least a scan chain having sub scan chains of stages to sequentially shift a test data in response to a clock signal in a scan path test mode, and each of the sub scan chains includes first flip-flops connected in series. A backup control circuit controls the target circuit and a memory such that a plurality of sub internal state data of a data indicating an internal state of the target circuit are stored as a plurality of write data in the memory in a save mode through the sub scan chains and the plurality of sub internal state data are read out from the memory as a plurality of read data and set in the sub scan chains in a restore mode.

Abstract: A semiconductor device includes a pair of transistors formed in a first conductive type semiconductor substrate. Each of the transistors contains a collector region of a second conductive type, opposite to the first conductive type, formed in the semiconductor substrate, a base region of the first conductive type formed in the collector region, and an emitter region of the second conductive type formed in the base region, the collector region of one transistor of the pair of transistors being separated from that of the other transistor. The semiconductor device further includes a first region of the first conductive type formed between the collector regions of the pair of transistors, and a buried layer of the second conductive type formed in the semiconductor substrate under the collector region of one transistor of the pair of transistors to connect the collector regions of the transistors therethrough.

Abstract: A semiconductor device 1 includes a semiconductor chip 10. Each of the semiconductor chips 10 includes a semiconductor substrate 12, a semiconductor layer 14 and an interconnect layer 16. The semiconductor substrate 12 has a specific resistance ?1 (first specific resistance). A semiconductor layer 14 is provided on the semiconductor substrate 12. Such semiconductor layer 14 exhibits a specific resistance ?2 (second specific resistance). The relationship of these specific resistances is: ?2<?1. The interconnect layer 16 is provided on the semiconductor layer 14. An inductor 18 for transmitting and receiving signals with an external element outside the semiconductor chip 10 is provided in the interconnect layer 16.

Abstract: A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and that has a copper area ratio that is greater than layers in which circuit interconnects are formed; and a lower copper layer that is electrically insulated from the upper copper layer and that is formed closer to the semiconductor substrate than the upper copper layer.

Abstract: A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a power-on-reset circuit that outputs a reset signal based on a detect signal representing that power is applied to the semiconductor integrated circuit; an initialization object circuit for which an initialization is performed based on the reset signal; and a power-on-reset monitor circuit that generates and outputs a power-on-reset monitor signal representing whether or not the initialization is performed normally, based on the reset signal output from the power-on-reset circuit and an output signal of the initialization object circuit for which the initialization is performed.

Abstract: Provided is a display method used for a display device that displays a design image and a pickup image in a superimposing manner, including: a distortion correction process of correcting distortion of the pickup image; an alignment process of aligning a position of the design image and a position of the pickup image; and a display process of displaying the design image and the pickup image in the superimposing manner. In the distortion correction process, the distortion of the pickup image is corrected so that a quadrangle formed by connecting four points on the pickup image becomes a rectangle in parallel with a vertical axis and a horizontal axis, the four points specified on the pickup image corresponding to four points on the design image which are connected to form a rectangle in parallel with the vertical axis and the horizontal axis.

Abstract: The invention provides a method of manufacturing a semiconductor device including a non-volatile memory with high yield, and a semiconductor device manufactured by the method. A method of manufacturing a semiconductor device includes a process of forming a second side wall such that the width of the second side wall, which is formed on the side of a portion of a second gate electrode that does not face dummy gates on a drain forming region side, in a gate length direction is larger than that of the second side wall, which is formed on the side of the second gate electrode on a source forming region side, in the gate length direction, in a non-volatile memory forming region.

Abstract: A semiconductor integrated circuit according to the invention has a plurality of output transistors connected to an output terminal through which output data is outputted, and an impedance control circuit and a slew rate control circuit. The impedance control circuit generates control signals specifying output transistors to be turned on when the output data is output, from among the plurality of output transistors. The slew rate control circuit generates, according to the control signals, drive signals driving the output transistors to be turned on, and variably sets respective delay times of the drive signals according to the control signals.

Abstract: A semiconductor switch according to an embodiment of the invention includes resistive members connected with a source and a drain witch are n-type diffusion layers formed in a P-well of an n-type MOSFET. When a gate of the n-type MOFET is turned off, a positive voltage is applied to a node between the resistive members for a reverse bias at a PN junction between the source and the drain, and the well. When the gate is turned on, the node between the resistive members is set to 0 V.

Abstract: A liquid crystal display device is composed of first and second data lines, first and second operational amplifiers, and a short-circuiting circuit. The first operational amplifier is configured to drive the first data line to a potential of a first polarity during a first period, and to drive the second data line to a potential to the first polarity during a second period following the first period. The second operational amplifier is configured to drive the second data line to a potential of a second polarity complementary to the first polarity during the first period, and to drive the first data line to a potential to the second polarity during the second period. The short-circuiting circuit is configured to short-circuit the first and second data lines during a short-circuiting period between the first and second periods.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: A liquid crystal display control circuit comprising a counter, inputted with a first signal for controlling a display status of a display unit and a second signal corresponding to an image data to be displayed on the display unit, for counting clocks for the second signal in 1 cycle of the first signal and for outputting the count value, a latch circuit for latching the number of clocks for the second signal included in 1 cycle of the first signal and for outputting the number of CLKs in 1 cycle, a reference count value circuit for generating a reference count value according to the number of CLKs in 1 cycle, and a comparator for generating a driver control signal that changes a current capacity of the driver unit according to the reference count value and the count value.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: The present invention provides a semiconductor device exhibiting an improved reliability of a bump coupling section. A semiconductor device is provided, which comprises: an interconnect layer; a stress-relaxing layer, covering the interconnect layer and provided with an opening exposing at least a portion of the interconnect layer; a post, covering the opening and provided so as to overlap with the stress-relaxing layer disposed around the opening; and a resin layer, provided around the post to cover the stress-relaxing layer, wherein a value of 2A/C is within a range of from 0.1 to 0.5, wherein C is a diameter of the post and 2A is a width of an overlapping region of the stress-relaxing layer with the post.

Abstract: A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.

Abstract: It is an object of the present invention to reduce output of a WAIT signal to maintain data consistency to effectively process subsequent memory access when there is no subsequent memory access in case of miss hit in a cache memory having a multi-stage pipeline structure. A cache memory according to the present invention performs update processing of a tag memory and a data memory and decides whether or not there is a subsequent memory access upon decision by a hit decision unit that an input address is a miss hit. Upon decision that there is a subsequent memory access, a controller outputs a WAIT signal to generate a pipeline stall for the pipeline processing of the processor to the processor, while the controller does not output a WAIT signal upon decision that there is no subsequent memory access.

Abstract: A semiconductor device includes an inductor configured to supply a current to a first node based on a higher voltage region power supply voltage. A first switch is configured to selectively supply a current from the first node into a third node based on a voltage on a second node; a second switch is configured to selectively supply a current from the first node into the second node based on a voltage of the third node; a third switch is configured to supply the current from the third node into a ground terminal based on a lower voltage region input logic level; and a fourth switch is configured to be turned ON/OFF alternately with the third switch to supply the current from the second node to the ground terminal.