Patents Assigned to NEC Electronics
  • Patent number: 7701726
    Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 20, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Jun Tsukano, Kenta Ogawa, Takehiko Maeda, Shintaro Yamamichi, Katsumi Kikuchi
  • Patent number: 7702009
    Abstract: A timing analysis apparatus in an integrated logical circuit according to the present invention includes a jitter information generation unit for generating period jitter information of an operational clock in response to a power supply/ground noise, a jitter information storage unit for storing the generated period jitter information, and a timing analysis unit for performing a timing analysis of the integrated logical circuit based on the stored period jitter information.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: April 20, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuya Akimoto
  • Patent number: 7701026
    Abstract: A backside imaging device includes a bump that is disposed overlapping with a sensor array region or a photodiode in a planar view. By this configuration, the bump becomes a support, and the semiconductor substrate is prevented from being damaged because of a bending applied to the semiconductor substrate.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 20, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Abiko
  • Patent number: 7701067
    Abstract: In an apparatus for manufacturing a semiconductor package including a semiconductor chip electronically and mechanically mounted on a tape-automated bonding tape, a resin potting unit is adapted to pot thermosetting resin into a gap between the semiconductor chip and the tape-automated bonding tape while the semiconductor chip and the tape-automated bonding tape are heated.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 20, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Mitsunobu Habe
  • Publication number: 20100090820
    Abstract: A data communication device includes: an antenna resonance circuit; a detection circuit; an arithmetic processing device; and a first switch. The antenna resonance circuit receives a signal in the ASK (Amplitude Shift Keying) format. The detection circuit demodulates a digital baseband signal based on the reception signal. The arithmetic processing device detects an appearance time of an edge in the demodulated digital baseband signal based on a preamble part of the reception signal. The first switch short-circuits both end of the antenna resonance circuit at first timing in synchronization with the appearance time of the edge.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 15, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Tomotake Oba
  • Publication number: 20100090710
    Abstract: The application methods in the related art cannot apply a sufficient voltage with a rectangular wave having a short rise time to an electronic circuit. Furthermore, electrostatic discharge test can apply a sufficient voltage but can only apply an oscillating waveform. A TLP generator is used as a rectangular wave generator. The sum of an injection resistance and a matching resistance is set so as to match the characteristic impedance of a transmission line for transmitting a rectangular wave to a test target. A capacitor is connected to a return line of the applied rectangular wave. With this configuration, stable application can be achieved. An error observation function of an electronic circuit gradually increases a peak value of the rectangular wave and determines the immunity based on an application voltage to cause an error for the first time.
    Type: Application
    Filed: March 6, 2008
    Publication date: April 15, 2010
    Applicants: NEC Corporation, NEC Electronics Corporation, Hanwa Electronic Ind. Co., Ltd.
    Inventors: Tsuneo Tsukagoshi, Takeshi Watanabe, Toshiyuki Nakaie, Nobuchika Matsui
  • Publication number: 20100090754
    Abstract: A boosting circuit includes a charge pump circuit; and a power supply circuit configured to supply a power supply voltage to the charge pump circuit. The power supply circuit includes an N-channel transistor connected with a power supply terminal of the charge pump circuit; and a current control circuit configured to control current flowing between the N-channel transistor and the charge pump circuit through the power supply terminal.
    Type: Application
    Filed: October 9, 2009
    Publication date: April 15, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Akiko Furuya, Yasuhiro Tonda
  • Patent number: 7696803
    Abstract: A signal generating circuit includes an input stage delay circuit which can switch a state of outputting a reference clock and a state of outputting a signal delaying the reference clock by a first time which is shorter than one cycle of the reference clock, a control section including a gate circuit holding the output of the input stage delay circuit for a second time which is shorter than one cycle of the reference clock from a point at which the output of the input stage delay circuit is changed to output a signal corresponding to the output of the gate circuit, and an output stage delay circuit outputting a signal delaying the output signal of the control section by the second time, in which the input stage delay circuit switches an output state in response to change of the output signal of the control section.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Osamu Arisaka
  • Patent number: 7696910
    Abstract: According to one aspect of the present invention, there is provided a dither circuit including a dither generating circuit generating a plurality of complementary signal pairs, and a dither input circuit generating a plurality of dither signals from the plurality of complementary signal pairs to add the generated dither signals to an analog input signal, in which the plurality of complementary signal pairs have different frequencies with each other, the dither input circuit includes capacitors provided for each of the plurality of complementary signal pairs and a plurality of switch pairs including first and second switches having one terminals connected to each one terminal of the capacitors, and the other terminals of the capacitors are connected to an adding point to the analog input signal, the first switch supplies ones of the complementary signal pairs to one terminals of the capacitors when a clock signal is in effective state, and the second switch supplies the others of the complementary signal pairs
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuhiro Koyama
  • Patent number: 7697592
    Abstract: A spread spectrum clock generator capable of generating a smooth spread spectrum clock while suppressing an increase in the size of the circuitry includes a phase interpolator, receiving a clock signal from a clock input terminal and a control signal (an up signal and/or down signal) are input, for adjusting the phase of an output clock signal in accordance with the control signal and outputting the resultant clock signal, and a control circuit for counting the clock signal that enters from the clock input terminal and outputting the control signal to the phase interpolator, the control signal varying the phase of the output clock signal based upon the count result. The phase of the output clock signal from the phase interpolator varies with time and is frequency-modulated within a prescribed frequency range.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazuo Ogasawara
  • Patent number: 7696061
    Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Ninomiya
  • Patent number: 7696789
    Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naohiro Matsui
  • Patent number: 7696793
    Abstract: A differential signal driver circuit is provided with a driver circuit and a common feedback circuit. The driver circuit is responsive to differential input signals for generating differential output signals from operation currents generated by two current sources. The common feedback circuit controls the current sources to regulate the current levels of the operation currents in response to the differential output signals.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Souji Sunairi
  • Patent number: 7696911
    Abstract: Disclosed is a digital-to-analog conversion circuit in which first and second serial DACs and an amplifier circuit for driving a data line are provided. In a first data period, the first serial DAC converts a first digital signal received in the first data period to a first signal, the second serial DAC holds a signal obtained by converting a digital signal received in a data period one period before the first data period, and the amplifier circuit amplifies and outputs the signal held in the second serial DAC, to the data line. In a second data period following after the first data period, the second serial DAC converts the second digital signal received in a second data period, the first serial DAC holds the first signal converted in the first data period, and an amplifier circuit amplifies and outputs the first signal held in the first serial DAC, to the data line.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Patent number: 7697044
    Abstract: The image processing apparatus includes an RGB-YUV converter for converting a color image into a luminance signal and a color difference signal and a YUV false color remover for removing false color based on the luminance signal Y and the color difference signals U, V. The false color remover includes an edge intensity calculator for calculating edge intensity based on the luminance signal Y, a modulation coefficient calculator for calculating a modulation coefficient so that a degree of modulation is greater as the edge intensity is higher, and a UV modulator for modulating a color difference signal having a value smaller than a prescribed threshold based on the degree of modulation.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kazuki Mishina
  • Patent number: 7697356
    Abstract: A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the GND potential. Then, the method performs a function test of reading data from memory cells by applying a potential higher than the GND potential to the backgate.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Naoto Akiyama
  • Patent number: 7696045
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask used as an etching mask to form a trench; forming a second insulating film on a surface of an inner wall of the trench with the mask used as a selective oxidation mask; removing the mask; forming a conductive film on the semiconductor substrate to fill the trench with the conductive film; and etching back the conductive film until at least a surface of the semiconductor substrate is exposed.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Minoru Kawahara
  • Patent number: 7698670
    Abstract: In a method for designing a semiconductor integrated device, there are prepared a first power supply cell having a first decoupling capacitance and a second power supply cell having a second decoupling capacitance larger than the first decoupling capacitance. One of the first and second power supply cells is arranged in each of power supply cell areas of an input/output circuit area of the semiconductor integrated device in accordance with frequency-to-impedance characteristics at a predetermined point of input/output buffers of the input/output circuit area between first and second power supply lines thereof and frequency-to-noise current characteristics of the input/output buffers of the input/output circuit area between the first and second power supply lines.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshihiro Masumura
  • Patent number: 7697064
    Abstract: To provide a video signal processing apparatus capable of generating video signals that enable displaying and recording of a high-quality picture. A video signal processing apparatus according to an embodiment of the present invention includes a decoder decoding an input TS to generate a video signal having a field frequency fv of 60 Hz or a video signal having a field frequency fv of 59.94 Hz, and a converter converting the respective video signals into NTSC video signals having a color subcarrier the phase of which is inverted for each frame.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Yoshikazu Komatsu
  • Patent number: 7696970
    Abstract: A driving circuit according to an embodiment of the invention includes: a switching unit for sequentially switching between a first operation of applying a positive gray-scale voltage to odd-numbered data lines and applying a negative gray-scale voltage to even-numbered data lines and a second operation of applying a negative gray-scale voltage to odd-numbered data lines and applying a positive gray-scale voltage to the even-numbered data lines; a plurality of short-circuit switches for short-circuiting a pair of adjacent odd-numbered data lines and a pair of adjacent even-numbered data lines to produce a plurality of pairs of short-circuited data lines in a switching period between the first operation and the second operation; and a plurality of common node-connected switches corresponding to the plurality of data line pairs and short-circuiting a corresponding one of the data line pairs to a common node.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 13, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Junya Yokota