Abstract: Disclosed is a circuit in which for conducting the scan path test, test clock terminals are provided in a number smaller than that of user clock domains, and a test clock control circuits on respective test clock lines to control whether the pulses of the test clock are propagated or blocked.

Abstract: A host device according to an embodiment of the present invention sends to a plurality of device units a specific token packet including address information of a first device unit and a general token transmission time derived from an execution time of a plurality of consecutive transactions upon execution of the plurality of consecutive transactions with a first device unit out of the plurality of device units. The first device unit receives the specific token packet to execute the plurality of transactions. The plurality of device units other than the first device unit receive the specific token packet to shift to and stay in a suspend state until the general token transmission time elapses, and then shift to a waiting state after the general token transmission time.

Abstract: Provided is a semiconductor device including a substrate, a gate insulating film which is formed on the substrate, and a gate electrode which is provided on the gate insulating film. The gate electrode includes a first metal silicide including a first metal material, and a second metal silicide including one of a second metal material and the second metal material in a contact portion between the gate insulating film and the gate electrode. The second metal silicide including the second metal material is a metal-rich silicide in which the composition ratio of the second metal material to silicon in the second metal silicide including the second metal is greater than 1.

Abstract: A data line driving circuit for a liquid crystal display device comprising: a plurality of first data lines applied with a positive potential, a plurality of second data lines applied with a negative potential, comparison units that compare with a reference voltage at least one of a potential at a first common line connected to the plurality of first data lines and a potential at a second common line connected to the plurality of second data lines, and switches that are controlled so that the first data lines and the second data lines are set to a connection state or an interruption state according to a comparison result by the comparison units.

Abstract: A method of forming an insulating film according to one embodiment of the present invention, which is a method of forming an insulating film for use in a semiconductor device, performs thermal oxidation of a tantalum nitride film at a temperature range of 200 to 400 degrees centigrade by a wet oxidation process, whereby a tantalum oxide film is formed as the insulating film.

Abstract: An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as seen from the direction normal to the plane. The lowermost vias are disposed so as to fit in a 4-row, 1-column rectangle, and the uppermost vias are disposed so as to fit in a 2-row, 2-column rectangle. The center of a via unit, which comprises the uppermost vias, as seen from the direction normal to the plane is disposed at the intersecting portion of the lowermost wiring layer and uppermost wiring layer. The center of a via unit, which comprises the lower vias, as seen from the direction normal to the plane is offset by a prescribed amount from the center of the via unit, which comprises the uppermost vias, as seen from the direction normal to the plane.

Abstract: A reliable semiconductor device including support bumps so as to adequately seal the region between the chips is to be provided. The semiconductor device includes a semiconductor chip; a bump formed on an upper face of the semiconductor chip; and a plurality of support bumps formed along a circumference of the region where the bump is provided, formed on the upper face of the semiconductor chip; and a flow path for a sealing resin is provided between the plurality of support bumps, so as to connect the region where the bump is provided and a periphery region of the semiconductor chip.

Abstract: In a semiconductor integrated circuit device including a charge pump circuit flowing an operating current therethrough, a current circuit is adapted to receive the operating current and a substantially constant current and generate an inverse current relative to the operating current and the substantially constant current.

Abstract: In the conventional technology, a region of larger data rate causes a varied level of the light exposure in the lithographic operation in the process for manufacturing the semiconductor device, causing a problem of allowing narrower process window. A semiconductor device includes interconnects (first interconnects) elongating along a first direction in a substrate surface of the substrate (transverse direction in the diagram), interconnects (second interconnects), elongating along the interconnects, and being spaced apart from the interconnects in plan view, and slit vias (slit-shaped via plugs), elongating along a second direction (longitudinal direction in the diagram) of directions in the substrate surface of the above-described substrate, which is a direction normal to the first direction, and being capable of electrically coupling the interconnect to the interconnect.

Abstract: A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.

Abstract: Disclosed is a receiving device which comprises first and second AD converters for inputting a received analog signal and converting the analog signal to digital signals in response to sampling clock signals of mutually different phases, first and second adaptive equalizers for respectively receiving outputs of the first and second AD converters, third and fourth adaptive equalizers for respectively receiving outputs of the second and first AD converters, a first adder for adding the outputs of the first and second adaptive converters, a second adder for adding the outputs of the third and fourth adaptive equalizers, a first decision unit for receiving the output of the first adder, deciding a received symbol for output, and outputting a decision error, a second decision unit for receiving the output of the second adder, deciding a received symbol for output, and outputting a decision error, and a multiplexing circuit for multiplexing the received symbols output from the first and second decision units, for o

Abstract: The semiconductor device has a fuse and a fuse opening created above the fuse. The fuse is divided into a plurality of lines at a crossing portion where the fuse crosses with an edge of the fuse opening. The plurality of divided lines of the fuse 101 are in parallel with each other and in perpendicular to the edge of the fuse opening.

Abstract: Provided is a highly reliable multi-bit memory cell capable of miniaturization including: a semiconductor substrate with a channel formed therein; diffusion layers arranged at two sides of the channel, for serving as source/drain; an insulating film arranged on a part of the channel; a trap film made of an insulating material having an electron trapping characteristic, arranged on the semiconductor substrate, the diffusion layers and the insulating film, and including trap regions each capable of trapping electrons in at least areas in contact with the semiconductor substrate at two sides of the insulating film; and a gate electrode arranged on the trap film. The trap regions are also formed on side surfaces of the insulating film, and the trap film has a structure in which the trap film is bent upward from the surface of the semiconductor substrate in the trap regions due to the insulating film.

Abstract: A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit.

Abstract: There is provided a semiconductor device excellent in reliability. The semiconductor device is comprised of a semiconductor substrate, an insulating portion having a multilayer insulating film composed of an etch stopper film, an insulating film, an etch stopper film, an insulating film, an etch stopper film and an insulating film provided on an upper portion of the semiconductor, fuses provided on the insulating portion, and a seal ring composed of a copper containing metal film, a barrier metal film, a copper containing metal film and a barrier metal film embedded in the insulating portion so as to surround a region just below the fuses.

Abstract: A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a specified row address on the first cell array with word lines corresponding to a specified row address on the second cell array.

Abstract: Disclosed is a D/A converter including: a delta-sigma modulator for subjecting a digital signal to delta-sigma modulation; a pulse-width modulator for outputting a pulse-width-modulated signal having a pulse width conforming to a digital value that is output from the delta-sigma modulator; and a distortion detector for detecting a distortion component produced in the pulse-width modulator. The distortion detector includes a delay controller for receiving the digital signal and correcting the phase thereof; a second delta-sigma modulator; a second pulse-width modulator; a subtractor for subtracting the output of the second delta-sigma modulator from the output of the second pulse-width modulator; and a second subtractor for subtracting the output signal of the first subtractor from the output signal of the delay controller.

Abstract: A data processing apparatus includes a memory, an additional bit generating unit which generates an additional bit to be added to write expectation values, on a basis of the write expectation values to be written respectively to designated addresses in the memory, the additional bit and the write expectation values being supplied to the memory as write data and stored respectively in memory cells at the addresses, and a write state judging unit which reads stored data retained in the memory cells at the addresses and judges a write state of the memory cells.

Abstract: A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal TSEL designating a hardware thread to be executed in a next execution cycle, a first selector that outputs an instruction generated by a hardware thread selected according to the thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein the thread scheduler specifies execution of at least one hardware thread selected in a fixed manner in a predetermined first execution period, and specifies execution of an arbitrary hardware thread in a second execution period.

Abstract: A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread.