Patents Assigned to NEC Electronics
-
Patent number: 7687864Abstract: Disclosed are a design method and apparatus in which information regarding a cell is input, the cell having taps in a substrate surface, for supplying the potentials of respective ones of wells in which active elements are formed, and source diffusion regions in the substrate surface, conductivity types thereof being opposite those of the wells. The taps are converted to conductivity types identical with those of the source diffusion regions to obtain source regions and freely set the well potentials of the cell to any potentials. If the cell is one having shorting portions electrically connecting taps and sources and the shorting portions are diffusion regions of the same conductivity type as that of the taps, then the shorting portions are converted to conductivity types identical with those of the source diffusion regions to obtain source regions.Type: GrantFiled: March 9, 2006Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventor: Hiroshi Yamamoto
-
Patent number: 7687803Abstract: A semiconductor device includes a semiconductor chip and a wiring substrate. The wiring substrate is configured to be electrically connected to the semiconductor chip, and have a plurality of terminals arranged on an surface opposite to a surface on which the semiconductor chip is mounted. The plurality of terminals includes a plurality of first terminals configured to be arranged closely to each other, and a plurality of second terminals configured to be arranged so as to surround the plurality of first terminals. The plurality of second terminals is provided such that terminals of the semiconductor chip are connected to outer terminals through the plurality of second terminals. Each of the plurality of first terminals is not provided with a metal ball, while each of the plurality of second terminals is provided with a metal ball.Type: GrantFiled: June 8, 2006Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Naohiro Takagi, Yasuhiro Suzuki, Kazuaki Satou
-
Patent number: 7687918Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.Type: GrantFiled: December 22, 2003Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki
-
Patent number: 7689808Abstract: A data processor includes a reader for reading a bit stream stored in a storage if there is free space of 8 bits or more in a buffer and outputting to a first array changer, the first array changer for changing an array sequence of the 8 bits in reversed sequence for a PNG bit stream but does not change the array sequence for a JPEG bit stream, a second array changer for further changing the array sequence of the 8 bits to output in case of PNG but outputting as it is in case of JPEG when reading out fixed length data of 8 bits from the buffer to the second processor, and a first processor for reading bits of VLC by 10 bits each from the buffer.Type: GrantFiled: April 24, 2007Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventor: Akihisa Ono
-
Patent number: 7688636Abstract: A semiconductor device comprises a first memory cell comprising more than seven transistors and storing data in a latch circuit; and a second memory cell storing data in a capacitor; a sense amplifier having about the same circuit configuration of the first memory cell and detecting data stored in the second memory cell.Type: GrantFiled: November 20, 2007Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventor: Hiroyuki Takahashi
-
Patent number: 7688109Abstract: The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted.Type: GrantFiled: June 11, 2008Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Junji Monden, Naoichi Kawaguchi
-
Patent number: 7687917Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.Type: GrantFiled: August 28, 2003Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyuki Yamanishi
-
Patent number: 7688140Abstract: Disclosed is a differential amplifier circuit that comprises: a first differential pair of a first conductivity type having an input pair connected to respective input terminals and an output pair connected to a load-element pair; a second differential pair of a second conductivity type having an input pair connected to the respective input terminals and an output pair connected to a load-element pair; a first output transistor connected between a first power supply and an output terminal and having a control terminal connected to a first output of the first differential pair; and a second output transistor connected between a second power supply and the output terminal and having a control terminal connected to a first output of the second differential pair.Type: GrantFiled: September 28, 2007Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventor: Tachio Yuasa
-
Patent number: 7688143Abstract: Disclosed is a variable gain circuit including a gain change region in which the gain is changed substantially exponentially as a function of a control voltage. The gain is changed in the gain change region substantially exponentially based on a function {(1+x)2+K}/{1?x}2+K}, where x is a control voltage and K is a parameter of K?1. The parameter K of the function is about equal to 0.21. The denominator and the numerator of the function are proportionate to driving currents of OTAs (operational transconductance amplifiers). Or, the denominator and the numerator of the above function are constituted by output currents of a MOS differential pair and a quadritail cell that includes four transistors driven by a common tail current. Outputs of two of the transistors, receiving a differential input voltage, are connected in common and outputs of the other two of the transistors, receiving the common mode voltage of the differential input voltage, are connected in common.Type: GrantFiled: April 10, 2008Date of Patent: March 30, 2010Assignee: NEC Electronics CorporationInventor: Katsuji Kimura
-
Publication number: 20100072578Abstract: A semiconductor chip which includes an element forming region formed over a substrate, a scribe line region which surrounds the element forming region, and a structure provided locally inside the scribe line region in at least one corner area of the semiconductor chip. The element forming region and the scribe line region include a plurality of interlayer dielectric films laminated over the substrate. The structure is constituted of corner pads sandwiching at least one of the interlayer dielectric films vertically in the direction of lamination, and vias interconnecting the corner pads.Type: ApplicationFiled: September 14, 2009Publication date: March 25, 2010Applicant: NEC Electronics CorporationInventor: Hiroyuki Kunishima
-
Publication number: 20100076580Abstract: A semiconductor integrated circuit design method, includes modeling a layer thickness of a wiring by a function including as independent variables, a percentage of surface area of the wiring in a first two-dimensional region where the wiring is formed, and a percentage of surface area for elements other than the wiring in a second two-dimensional region, and designing the wiring based on the wiring modeled.Type: ApplicationFiled: September 11, 2009Publication date: March 25, 2010Applicant: NEC Electronics CorporationInventor: Hiroshi Kitahara
-
Publication number: 20100073982Abstract: Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.Type: ApplicationFiled: July 8, 2009Publication date: March 25, 2010Applicant: NEC Electronics CorporationInventors: Shinobu Asayama, Toshio Komuro
-
Patent number: 7682880Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.Type: GrantFiled: March 14, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Hidekazu Kawashima, Tetsuya Katoh
-
Patent number: 7683871Abstract: A display control device of the present invention includes a gamma circuit producing and outputting a gray scale voltage and a selection drive circuit selecting the gray scale voltage on the basis of a pixel data displayed on a display device and outputting the selected gray scale voltage as a pixel driving signal to the display device. The selection drive circuit includes an analog memory and holds the selected gray scale voltage in the analog memory.Type: GrantFiled: February 27, 2006Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Fumihiko Kato
-
Patent number: 7683485Abstract: When a BGA package device is mounted to another substrate and tested for packaging strength, solder balls (8) frequently come detached in places where the edges of a semiconductor chip (1) align with the centers of the solder balls (8) on a BGA substrate (9) in the perpendicular direction of the substrate. In a semiconductor device of the present invention, the center of a semiconductor chip and the center of a BGA substrate to which the chip is mounted do not coincide with each other, and edges of the semiconductor chip do not align with the ball center positions on the BGA substrate in a direction perpendicular to the chip.Type: GrantFiled: February 15, 2008Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Hirofumi Nikaido
-
Patent number: 7683687Abstract: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.Type: GrantFiled: November 7, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Shinji Kawashima, Kazunori Doi
-
Patent number: 7683819Abstract: Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.Type: GrantFiled: February 15, 2008Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Akira Kurauchi
-
Patent number: 7684270Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Takuya Hirota, Takao Yanagida, Hiroyuki Takahashi
-
Patent number: 7683600Abstract: An output circuit in accordance with one embodiment of the present invention includes: an input terminal for receiving an input signal; an output transistor connected between a first power supply and an output terminal; a current control circuit connected to the input terminal and the output transistor for controlling current outflow and inflow for the gate of the output transistor based on the input signal; a voltage generating circuit connected to the first power supply; and a switch circuit coupled between the gate of the output transistor and the voltage generating circuit, the switch circuit having alternatively an on state and an off state thereof in response to the input signal; wherein the switch circuit becomes the off state when the potential difference between the gate of the output transistor and the first power supply becomes equal to or below a predetermine value regardless of the voltage level of the input signal.Type: GrantFiled: April 16, 2008Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Jiro Kanamaru, Toshiaki Akioka
-
Patent number: 7684451Abstract: An optical transmitter module includes a semiconductor laser for outputting forward outgoing light and backward outgoing light, a temperature control device for controlling a temperature of the semiconductor laser, a beam splitter plate for receiving incidence of the backward outgoing light and outputting split light, which is reflected part of the backward outgoing light and transmitted light, which is part of the backward outgoing light, a first photoelectric conversion element for converting the split light into an electric signal. The beam splitter plate includes an anti-stray-light structure for preventing the transmitted light reflected by an incident surface of a wavelength filter from entering the first photoelectric conversion element through a side end surface portion of the beam splitter plate.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventor: Shigenori Satou