Abstract: A Direct Memory Access (DMA) device includes a first buffer which holds a first transfer information required for a first transfer request, and a second buffer which holds a second transfer information required for a second transfer request, and a transfer request comparison circuit which determines whether or not a current transfer request, which is newly inputted, matches with the first transfer request or the second transfer request.

Abstract: There is provided a semiconductor storage device including a substrate area, a first and a second isolation area, a first well area where the first transistor is placed, a second well area where the second transistor to output a first voltage to bring the first transistor into non-conduction is placed, and a third well area where the third transistor to output a second voltage to bring the first transistor into conduction is placed. The second and third well areas and the second isolation area are formed between two of the first well area, the second isolation area is formed between the second well area and one of the first well area, and the third well area is formed between the second well area and another one of the first well area.

Abstract: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.

Abstract: In relation to the conventional semiconductor device provided with a plurality of FETs, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region (certain region). The four have each of gate electrodes, respectively. Each of the gate electrodes are arranged along a circle in this sequence in plan view. The four FETs have the substantially same geometry.

Abstract: A differential signal receiver according to the present invention includes a waveform shaping circuit selectively outputting an upper limit value having a first potential difference from a first power supply potential, and a lower limit value having a second potential difference from the upper limit value, from a first and a second output terminals according to a differential signal input, and an amplifier comparing voltages of the first and the second output terminals and outputting one of a voltage almost the same as the first power supply potential or a voltage almost the same as a second power supply potential.

Abstract: A semiconductor memory device is provided with a DRAM array and a control circuit. The DRAM array includes first and second storage areas. The control circuit controls an access to said DRAM array so that data hold characteristics of said first storage area are superior to those of said second storage area.

Abstract: A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.

Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

Abstract: Aiming at providing a semiconductor device capable of reducing the ON-resistance when voltage smaller than a predetermined value is applied to the base region and the drift region, and capable of increasing the ON-resistance so as to prevent thermal fracture when the voltage is not smaller than the predetermined value, and at providing a method of fabricating such semiconductor device, a P-type diffusion layer 7 is formed in an N-type drift region 2 of a semiconductor device 100, as being apart from a base region 5, wherein the diffusion layer 7 is formed in a region partitioned by lines L each extending from each of the intersections of the boundary B, between the drift region 2 and a base area 5A of the base region 5, and the side faces of a trench 15 surrounding the base area 5A of the base region 5, towards the bottom plane of the drift region 2 right under the base area 5A, while keeping an angle ?2 of 50° between the lines L and the boundary B.

Abstract: Disclosed is a synchronization signal detecting apparatus that includes a window generating circuit for generating a synchronization detecting window, a re-synchronization window generating circuit for generating a re-synchronization window, and a synchronization detecting circuit for generating a re-synchronization detecting window of a time interval that excludes a re-synchronization window mask from the re-synchronization window, detecting a synchronization signal from an input bit stream and detecting the synchronization signal in the re-synchronization detecting window. If the synchronization signal is detected in the re-synchronization detecting window without being detected in the synchronization detecting window a prescribed number of times in succession, the time interval of the re-synchronization window is updated.

Abstract: A transmitter of the invention, according to a first aspect, has first and second driving circuits with reverse-current prevention elements connected between output terminals and power supply terminals, and a control circuit which controls the outputs of the first and second driving circuits, the control circuit controlling the first and second driving circuits, during a transition from a first state in which the first and second driving circuits output a first or a second logic level to a second state in which the first and second driving circuits output an intermediate level between the first and second logic levels, to induce a third state in which a through current flows in the first and second driving circuits via the reverse-current prevention elements.

Abstract: A method of manufacturing a semiconductor device, which is capable of easily removing a sealing sheet building up terminal surfaces of leads, includes arranging, on molds, terminal surfaces of leads in a lead frame on which semiconductor elements are mounted so as to come in contact with a sealing sheet, pouring a resin into the molds to form a resin sealed body including the semiconductor elements, and cleaning the resin sealed body, and the cleaning of the resin sealed body ravels the sealing sheet by a cleaning solvent and removes the sealing sheet.

Abstract: In a design-system distributing method, when a server side design system is updated, a server compares an updated server side design system and a client update state data, and the server distributes an update assisting system, an update indication data and a difference data to a client system based on the comparing result. The client system stores the update assisting system, the update indication data and the difference data, and the client system starts the stored update assisting system such that an update notice is outputted to a user of the client system to urge update of the client side design system each time a preset condition is satisfied until an update command of the client side design system is supplied to the client system. The client system updates the client side design system based on the stored update indication data and the stored difference data in response to the update command.

Abstract: An SRAM includes a memory cell and a precharge circuit. The precharge circuit precharges a bit line pair with a power supply voltage before writing a data in the memory cell or before reading a data therefrom at a time of a normal mode, and which feeds a power supply voltage to at least a low level data-holding node of a node pair of the memory cell at a time of a read test mode, between time for writing a data in the memory cell and time for reading a data therefrom.

Abstract: A power supply controller includes an analog to digital (A/D) converter that performs analog-digital conversion of an output voltage and outputs a digital signal, a deviation signal generator unit that generates a deviation signal from the digital signal and a standard voltage value serving as an output voltage target value, and a power controller unit that controls the output voltage based on the deviation signal. The power supply controller includes a conversion range setting unit that sets a range of the reference voltage into the A/D converter based on a first signal as the digital signal in a power supply startup period, and sets the reference voltage range into the A/D converter based on a second signal as the deviation signal or as a signal corresponding to the deviation signal in a steady state period.

Abstract: A test circuit according to the present invention includes: a synthesis circuit that synthesizes a first test result signal output from a first test target circuit in response to a test instruction, and a second test result signal output from a second test target circuit in response to the test instruction; an inter-block delay generation circuit that delays the second test result signal with respect to the first test result signal; and a test result holding circuit that holds a synthesized test result signal every predetermined timing, the synthesized test result signal being output from the synthesis circuit

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: In an evaporator for evaporating mists of liquid raw material to thereby generate start gas for layer-formation, an evaporator body has an evaporator chamber defined therein, and a mist supply throat for introducing the mists into the evaporating chamber. The evaporator chamber is defined by a principal evaporating face which opposes to the mist supply throat. The evaporator body also has a start-gas supply passage which is formed therein between the mist supply throat and the principal evaporating face such that the start gas flows out of the evaporating chamber through the start-gas supply passage. A ridge member is provided on an inner side wall surface of the evaporating chamber between the start-gas is supply passage and the principal evaporating face so that a tip edge of the ridge member is directed to the principal evaporating face.

Abstract: A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

Abstract: Disclosed is a clock-and-data recover circuit in which a data sampling circuit, a phase comparator, a phase controller and a phase interpolator make up a loop. The data sampling circuit samples serial input data, and the phase comparator receives an output from the data sampling circuit to detect the phase relationship between clock and the data. The phase controller outputs a phase control signal based on the result of phase comparison of the phase comparator to output a phase control signal. The phase interpolator receives a multi-phase clock composed of plural clock signals with different phases and supplies a clock signal having the phase interpolated based on the phase control signal, to the data sampling circuit. The clock and data recovery circuit further includes a second phase interpolator and a second data sampling circuit. The phase controller generates and outputs a second phase control signal to the second phase interpolator.