Patents Assigned to NXP
  • Patent number: 10241151
    Abstract: A die crack detector and method are provided. A first metal trace is formed over a substrate with the first metal trace configured to extend around a perimeter of a semiconductor die. A second metal trace is formed over the first metal trace with the second metal trace configured to overlap the first metal trace. A dielectric material is disposed between the first and second metal traces. A first detector terminal is coupled to the first metal trace and a second detector terminal coupled to the second metal trace. The detector terminals are configured to receive a predetermined voltage.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Jose Luis Suarez, Michele Lynn Miera
  • Patent number: 10243937
    Abstract: A method of performing an equality check in a secure system, including: receiving an input v having a known input property; splitting the input v into t secret shares vi where i is an integer index and t is greater than 1; splitting an input x into k secret shares xi where i is an integer index and k is greater than 1; splitting the secret shares xi into a s chunks resulting in s·k chunks yj where j is an integer index; calculating a mapping chain t times for each secret share vi, wherein the mapping chain including s·k affine mappings Fj, wherein yj and Fj?1(yj?1) are the inputs to Fj and the F0(y0)=vi; and determining if the outputs have a known output property indicating that the input x equals a desired value.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: March 26, 2019
    Assignee: NXP B.V.
    Inventor: Wilhelmus Petrus Adrianus Johannus Michiels
  • Patent number: 10242988
    Abstract: An integrated circuit (IC) system includes a substrate, a first doped well of a first polarity in the substrate, a first electrode in contact with the doped well, a buried oxide (BOX) in contact with the doped well in the substrate, a first IC device including a second electrode formed on the BOX, and fuse control circuitry coupled to the first electrode and the second electrode. The fuse control circuitry is configured to cause voltages to be applied to the first and second electrodes to change a resistance level of the BOX in the vicinity of the second electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventor: Mark Douglas Hall
  • Patent number: 10241946
    Abstract: A method, system, and apparatus are provided for managing multiple DMA channels in different DMA modes by processing command sequences associated with different virtual DMA channels and stored in a command queue structure, such that a first command sequence is processed to directly configure one or more first register descriptors at a context store to implement a direct configuration DMA mode for a first virtual channel, a second command sequence is processed to initiate a fetch of a linked list descriptor chain for loading one or more second register descriptors at a second DMA channel context store register to implement a link list configuration DMA mode for a second virtual channel, and a third command sequence is processed to retrieve an instruction program for loading into the command queue structure and execution by the DMA controller to implement a program configuration DMA mode for a third virtual channel.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael J. Rochford, Rabindra Guha, Daniel C. Laroche, Malcolm D. Stewart
  • Patent number: 10243533
    Abstract: Aspects are directed to an amplifier circuit including a signal processing circuit and a calibration circuit. In certain specific embodiments, the signal processing circuit includes a signal combiner and a closed-loop feedback path, and the signal processing circuit is designed to provide a loop transfer function for a derived signal partly representing contributions from an audio input signal, a control or pilot signal having a target frequency range, and a calibration signal. The signal combiner is designed to combine aspects of the control or pilot signal and aspects of the audio input signal, and the calibration circuit is designed to adjust an effective gain of the derived signal in response to whether a unity-gain frequency of a signal in the closed-loop feedback path, as provided via the loop transfer function, is higher or lower than the target frequency range.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 26, 2019
    Assignee: NXP B.V.
    Inventors: Marco Berkhout, Fred Mostert, Massimo Ciacci, Mattheus Johan Koerts, Martin Kessel
  • Patent number: 10239494
    Abstract: A secure vehicle access system comprises a vehicle and a key associated with the vehicle. The key comprises: a radio frequency, RF, key transceiver configured to: broadcast at least one signal; and listen for an acknowledgement message from the vehicle. The vehicle comprises: a radio frequency, RF, vehicle transceiver configured to: listen for the at least one broadcast signal from the key; and in response thereto, transmit an acknowledgement message back to the key to establish a communication link between the vehicle and the key. The key further comprises a ranging circuit configured to perform a distance determination between the vehicle and the key, following the establishment of the communication link, to determine whether to allow access to the vehicle.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP B.V.
    Inventor: Bernhard Spiess
  • Patent number: 10243410
    Abstract: According to a first aspect of the present disclosure, an electronic device is provided, comprising: a first power extraction unit configured to extract a first amount of power from an RF field present on the RF antenna and to provide said first amount of power to one or more circuits of the electronic device; a second power extraction unit configured to extract a second amount of power from the RF field and to provide said second amount of power to an output of the electronic device; a control unit configured to control the second amount of power provided to said output. According to a second aspect of the present disclosure, a corresponding power management method for use in an electronic device is conceived. According to third aspect of the present disclosure, a corresponding non-transitory computer-readable medium comprising instructions is provided.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP B.V.
    Inventor: Jaydeep Girishkumar Dalwadi
  • Patent number: 10242979
    Abstract: A device includes an integrated circuit (IC) layer, an insulative layer such as a buried oxide (BOX) layer, a substrate layer separated from the IC layer by the insulative layer, and a set of protective components such as a set of Zener diodes or a Zener stack coupled to the IC layer to protect the IC layer from transient electric events such as an electrostatic discharge (ESD), an inductive flyback, and a back electromotive force (back-EMF) event. The Zener stack has a Zener breakdown voltage greater than a breakdown voltage of the IC layer. An effective bias voltage has a voltage level less than the breakdown voltage of the IC layer. The Zener diode or Zener stack may be coupled to one or more isolation structures of the IC layer. The isolation structures separate the IC layer into electrically distinct portions or wells in which other electric components are formed.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventor: Willliam Ernest Edwards
  • Patent number: 10242355
    Abstract: A method for completing a transaction at a terminal between a terminal and a mobile device including: initiating a transaction at the terminal; initiating communication with the mobile device; determining that the mobile device is without power; transmitting a wireless power signal to power the mobile device; sending a transaction authentication request message to the mobile device after transmitting the wireless power signal; receiving an authentication message from the mobile device; and completing the transaction after receiving the authentication message from the mobile device.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 26, 2019
    Assignee: NXP B.V.
    Inventors: Kai Neumann, Johannes van Lammeren, Klaas Brink
  • Patent number: 10236852
    Abstract: An integrated circuit (IC) includes an input pad and an output pad separated from the input pad by a predetermined distance. A plurality of capacitors are coupled in series between the input pad and the output pad. The plurality of capacitors are distributed to substantially span the predetermined distance. An inductor is formed from a bond wire, having a first end attached at the first input pad and a second end attached at the output pad. The inductor and plurality of capacitors configured to form a predetermined open circuit resonance.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 19, 2019
    Assignee: NXP USA, INC.
    Inventors: Joseph Gerard Schultz, Hussain Hasanali Ladhani, Enver Krvavac, Yu-Ting Wu
  • Patent number: 10237000
    Abstract: A method for compensating phase shift is provided. The method includes sweeping a transmitter (TX) clock frequency over a frequency range and sampling resistance values at a receiver (RX) circuit while sweeping the TX clock frequency. A first frequency in the frequency range is determined which corresponds to a maximum resistance value sampled at the RX circuit. Using a look-up table (LUT), a phase adjust value is determined based on the first frequency. A phase of the TX clock is adjusted based on the phase adjust value.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Martin Buchsbaum, Erich Merlin, Manuel Markus Figer
  • Patent number: 10235324
    Abstract: A method and apparatus provide an ability to selectively couple one of the output of the buffer or the output of the digital driver to a data terminal based upon a state of a storage location in which a stored first select indicator is stored and based upon a state of a selection signal. An external serial interface, at a semiconductor die, includes the data terminal, a selection terminal to receive the selection signal, and a clock terminal to receive a clock signal. A buffer includes an input to receive a secondary signal and an output to provide the secondary signal to the data terminal. A digital driver includes a digital output coupled to the data terminal. A first storage location has a storage state based upon the stored first select indicator. Select circuitry provides the selectively coupling.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: William E. Edwards, Jesse R. Beeker
  • Patent number: 10234881
    Abstract: A voltage regulator has a slow loop for providing a regulated DC current and a fast loop for providing a transient current. Feedback information is used to monitor the output voltage and control the current used to generate the output voltage. The voltage regulator does not need a capacitor to create transient current.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Shishir Goyal, Arvind Sherigar
  • Patent number: 10235506
    Abstract: A method of obscuring software code implementing a modular exponentiation function, including: receiving modular exponentiation parameters including an exponent e having N bits; generating a bitwise exponent array and inverse bitwise exponent array; and generating modular exponentiation function operations using the bitwise exponent array, inverse bitwise exponent array, and N, wherein the generated modular exponentiation function operations are split variable operations.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Jan Hoogerbrugge, Wil Michiels
  • Patent number: 10237063
    Abstract: A method of producing a secure integrated circuit (IC), including: loading the IC with a unique identification number (UID); loading the IC with a key derivation data (KDD) that is based upon a secret value K and the UID; producing a secure application configured with a manufacturer configuration parameter (MCP) and the secret value K and configured to receive the UID from the IC; producing a manufacturer diversification parameter (MDP) based upon the MCP and the secret value K and loading the MDP into the IC; wherein secure IC is configured to calculate a device specific key (DSK) based upon the received MDP and the KDD, and wherein the secure application calculates the DSK based upon the MCP, K, and the received UID.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventor: Jan Rene Brands
  • Patent number: 10236071
    Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van De Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • Patent number: 10237056
    Abstract: Various exemplary embodiments relate to a method of communicating by a transmitter. Embodiments of the method may include creating information to be used by a receiver to define a spreading sequence for a subsequent packet, coding the information into a current communications packet, and transmitting the current communications packet.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Andries Hekstra, Stefan Drude, Frank Leong, Arie Koppelaar
  • Patent number: 10236260
    Abstract: A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael B. Vincent, Gregory J. Durnan
  • Patent number: 10235225
    Abstract: A method of handling requests between contexts in a processing system includes, in a current context of a source processing system element (PSE): executing a send-and rendezvous instruction that specifies a destination PSE, a queue address in the destination PSE, a set of source registers, and a set of receive registers; and sending a send-and-rendezvous message (SRM) to the destination PSE, wherein the SRM includes an address of the destination PSE, a destination queue address, a source PSE address, and an identifier of the current context in the source PSE.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Peter J. Wilson, Brian C. Kahne
  • Patent number: 10236898
    Abstract: A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Didier Salle, Olivier Vincent Doare, Birama Goumballa, Cristian Pavao Moreira