Patents Assigned to NXP
  • Patent number: 9703603
    Abstract: A system for executing an accelerator call function includes a processor, a register context memory, an accelerator scheduler, multiple accelerator cores, and a stack memory. The processor executes a program task. The processor includes a register that stores task context information of the program task. The accelerator call function includes an accelerator operation. The processor forwards the accelerator operation to the accelerator scheduler. Concurrently, the processor stores the task context information in the register context memory. The accelerator scheduler identifies one of the accelerator cores and forwards the accelerator operation to the identified core. The identified core executes the accelerator operation, generates a return value, and stores the return value in the register context memory, which in turn provides the return value and the task context information to the processor.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Sourav Roy, Michael B. Schinzler
  • Patent number: 9703461
    Abstract: A method and apparatus for creating media content. The method comprises recording a video; while the video is being recorded, automatically analyzing the content of the video; and creating media content by editing the video, assisted by the results of the content-analysis. A user may not need to select in advance (that is, before the video is recorded) the type or format of media content to be created.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventor: Benoit Brieussel
  • Patent number: 9702958
    Abstract: A governing circuit for a magneto-transistor is disclosed. The magneto-transistor comprising a first and second collector. At least one emitter and at least one base. The governing circuit is configured to measure a first calibration current at the first collector of the magneto-transistor and a second calibration current at the second collector of the magneto-transistor, while a calibration base-emitter voltage is applied to the magneto-transistor. The magneto-transistor is also configured to measure a first measurement current at the first collector of the magneto-transistor and a second measurement current at the second collector of the magneto-transistor, while a measurement base-emitter voltage is applied to the magneto-transistor, wherein the measurement base-emitter voltage is different form the calibration base-emitter voltage and determine an output signal indicative of an applied magnetic field using the measured first and second measurement current and first and second calibration currents.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Victor Zieren, Robert Hendrikus Margaretha Van Veldhoven, Olaf Wunnicke, Hans Paul Tuinhout
  • Patent number: 9704850
    Abstract: An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate. The silicon controlled rectifier also includes a first p-type region located adjacent the first n-type region in the semiconductor substrate. The silicon controlled rectifier further includes an n-type contact region and a p-type contact region located in the first n-type region. The silicon controlled rectifier also includes an n-type contact region and a p-type contact region located in the first p-type region. The silicon controlled rectifier further includes a blocking region having a higher resistivity than the first p-type region. The blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Guido Wouter Willem Quax, Da-Wei Lai
  • Patent number: 9705502
    Abstract: An electrical system can selectively power a load via a USB connection or via another power source, such as a wireless power transfer path. An integrated switch controller determines whether to power the load via the USB connection or the other power sources and controls two external transistors via a single I/O pin connection to implement that determination. The switch controller determines the greater of two voltages: a voltage associated with the USB connection and a voltage associated with the other power source. The switch controller also determines whether there is a valid USB connection. The switch controller circuitry that controls the two external transistors is powered at the greater voltage to ensure that the external transistors are appropriately and securely turned on or off.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Yang Wang, Jie Jin, Jianzhou Wu
  • Patent number: 9703632
    Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 11, 2017
    Assignee: NXP B. V.
    Inventor: Steven Thoen
  • Patent number: 9704823
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
  • Patent number: 9704853
    Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Hubert M. Bode, Weize Chen, Richard J. De Souza, Patrice M. Parris
  • Patent number: 9704851
    Abstract: A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Gijs Jan De Raad, Guido Wouter Willem Quax
  • Patent number: 9705490
    Abstract: There is described a driver circuit for a single wire protocol slave unit, the driver circuit comprising (a) at least one current mirror comprising a first transistor (MP1, MN3) and a second transistor (MP2, MN4), wherein the gate of both transistors is connected to a bias node (PBIAS, S2BIAS), and wherein the second transistor is adapted to conduct a mirror current (I2, IOUT) equal to a current (I1, I2) conducted by the first transistor multiplied by a predetermined factor, (b) a bias transistor (MP3, MN5) for selectively connecting and disconnecting the bias node to and from a predetermined potential (VDD, GND) in response to a control signal (ABUF, AN), and (c) a current boosting element for providing a boost current (I1P, I2P) to the bias node for a predetermined period of time when the control signal causes the bias transistor to disconnect the bias node from the predetermined potential. There is also described a universal integrated circuit card device comprising a driver circuit.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Sunil Kasanyal, Kiran Gopal
  • Patent number: 9703056
    Abstract: A method and apparatus are provided for fabricating an electro-optical interconnect on an integrated circuit (101, 114) in which an optical circuit element (102) is formed by forming a cylinder-shaped conductive interconnect structure (120, 122, 126, 128) with one or more conductive layers formed around a central opening (129) which is located over an optically transparent layer (118) located over the optical circuit element (102).
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Sriram Neelakantan, Trent S. Uehling
  • Patent number: 9697118
    Abstract: A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Vivek Singh, Navdeep Singh Gill, Stephan M. Herrmann, Sumit Mittal
  • Patent number: 9698792
    Abstract: An electronic device includes multiple functional logic modules each having a corresponding settling time, a clock generator element, and multiple memory elements. The clock generator element generates multiple clock signals having clock periods of a common duration. Each clock signal has a first clock transition and a second clock transition during each clock period, and a latest second clock transition of the clock signals in a particular clock period precedes an earliest first clock transition in a subsequent clock period by the settling time. Each memory element is clocked by a respective one of the clock signals, and each memory element includes an input latch clocked on a first clock transition of the respective one of the clock signals, and an output latch clocked on a second clock transition of the respective one of the clock signals.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 4, 2017
    Assignee: NXP B.V.
    Inventor: Henri Verhoeven
  • Patent number: 9697163
    Abstract: A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 4, 2017
    Assignee: NXP USA, Inc.
    Inventors: Alistair Robertson, Manfred Thanner
  • Patent number: 9698116
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9698093
    Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 4, 2017
    Assignee: NXP USA,INC.
    Inventors: Chee Seng Foong, Ly Hoon Khoo, Wen Shi Koh, Wai Yew Lo, Zi Song Poh, Kai Yun Yow
  • Patent number: 9698749
    Abstract: An impedance matching device is presented. The device includes an input terminal configured to receive a radio frequency signal, and an output terminal configured to couple to an amplifier. The device includes an impedance prematch network coupled to the input terminal and the output terminal. The impedance prematch network includes a first inductor, such as a first wire bond. The device includes a resonator structure including a second inductor, such as a wire bond, inductively coupled to the first inductor.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventor: Nick Yang
  • Patent number: 9697065
    Abstract: A method for managing a reset process in a processing system is provided. The method includes enabling a watch dog unit based on a power-on reset (POR) event. A stuck in reset condition indication is received at the watch dog unit and used to determine whether the received reset condition indication corresponds to an unintentional reset condition. If the received reset condition indication is an indication of an unintentional reset condition, a watch dog POR trigger signal is generated and a reset state machine is repeated for system recovery.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 4, 2017
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Steven K. Watkins, Garima Sharda, James M. Giandelone, Stefano Pietri, Thomas H. Luedeke
  • Patent number: 9697897
    Abstract: A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael A Sadd, Anirban Roy
  • Patent number: 9698762
    Abstract: A flip-flop structure comprising a master latch and a slave latch. An output of an input stage of the master latch is coupled to the output of the master latch. The input stage is arranged to drive a logical state at the output of the master latch corresponding to a logical state of the received data input signal during a first phase of a clock signal. A feedback component is arranged to sample a logical state at the output of the master latch and to drive a logical state at the output of the master latch based on the sampled logical state at the output of the master latch such that the sampled logical state is maintained, during a second phase of the clock signal.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Vasily Vladimirovich Korolev, Alexander Ivanovich Kornilov, Victor Mikhailovich Mikhailov