Abstract: In an analog-to-digital converter (ADC) having storage capacitors, passive top-plate switch circuitry has at least one diode-configured transistor connected between a first transistor and the top-plate node of the storage capacitors to provide a diode-voltage drop that ensures that the voltage at the node between two transistors is different from the top-plate node voltage in order to reduce GIDL/GISL leakage current through the first transistor that could adversely affect the ADC's digital output value. A corresponding capacitor is connected across each diode-configured device to reduce the amount of charge needed to achieve intermediate-node, steady-state voltages when the switch circuitry is off. In an n-type implementation, a reverse-diode-biased isolation device is connected between the top-plate node and the at least one diode-configured device to prevent the top-plate node from seeing the large dynamic junction capacitance of the at least one diode-configured device.

Abstract: Various embodiments relate to a method, device, and non-transitory medium including: determining a master key value for use in secure communications with a different device, wherein the master key value is used as a master key; deriving at least one session key using the master key; generating a new master key value based on the master key; deleting the current master key value; and using the new master key value as the master key.

Abstract: A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.

Abstract: An error response method for a mixed criticality system includes assigning a safety level to an application executed by a processor. Executing the application includes a transaction between the processor and a resource. The safety level is stored at the resource. The safety level and a fault indication are transmitted from the resource to a fault collection and control unit (FCCU). The fault indication is responsive to a fault from the resource. The FCCU responds to the fault indication with an action determined by the safety level.

Abstract: Near-field communications (NFC) with NFC reader devices are facilitated. In accordance with one or more embodiments, an apparatus includes a NFC circuit that wirelessly communicates with different types of local NFC readers using an NFC protocol, a host circuit having one or more modules that communicate with one of the types of local NFC readers via the NFC circuit, and second (e.g., secure) modules that respectively communicate with a specific one of the different types of local NFC readers, also via the NFC circuit, using secure data stored within the second module. A routing circuit is responsive to an NFC communication received from a specific one of the NFC readers, by identifying one of the first and second modules that communicates with the specific one of the NFC readers, and routing NFC communications between the specific one of the NFC readers and the identified one of the modules.

Abstract: A monitoring device has an event monitor, an uplink interface to a chain controller device, and a downlink interface to a further monitoring device, and a daisy controller for coupling the uplink to the chain downlink. The event monitor, in response to detecting an event in sleep mode, generates a wake-up signal. The daisy controller sets the electronic monitoring device to a wake-up request mode and disables the bidirectional data communication via the downlink interface, and subsequently transmits a wake-up request to the chain controller device via the uplink interface. In response to receiving a wake-up command, the daisy controller re-enables the bidirectional data communication via the downlink interface and sets the electronic monitoring device to the operational mode. Thereby a wake-up sequence is performed while the wake-up request mode avoids bus conflicts.

Abstract: A loudspeaker controller (1) for controlling a loudspeaker (2), configured to determine time-varying impedance information of the loudspeaker (2) based on a loudspeaker voltage and a measure of a loudspeaker current and provide for control of the loudspeaker (2) in accordance with said time-varying impedance information.

Abstract: An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.

Abstract: A method and circuit for controlling current through an inductive load such as an electromagnetic valve of a vehicle anti-lock braking system includes first and second driver stages, controlled by PWM (pulse width modulation) signals, for providing, respectively, an actuation path for valve current in an “on” phase and a recirculation path for valve current in an “off” phase. A peak value of current flowing in the actuation path at the end of an “on” phase is compared with a peak value of current flowing in the recirculation path at the start of the “off” phase in order to detect any malfunction of the circuit. An embodiment of the invention has the advantage of being able to detect any malfunction at very low and very high PWM duty cycles.

Abstract: A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.

Abstract: A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage.

Abstract: A memory device includes a volatile memory cell and a non-volatile memory cell. The non-volatile memory cell includes a first resistive element having a first terminal and a second terminal and a second resistive element having a first terminal and a second terminal. The first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node. The second terminal of the first resistive element is coupled to a first source line voltage. The second terminal of the second resistive element is coupled to a second source line voltage. A first transistor includes a first current electrode coupled to a first data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node.

Abstract: The embodiments described herein provide class F amplifiers and methods of operation. So implemented, the class F amplifiers can be used to provide high efficiency amplification for a variety of applications, including radio frequency (RF) applications. In general, the class F amplifiers are implemented with at least one transistor and an output matching network, where the output matching network includes a plurality of resonant circuits configured to facilitate class F amplifier operation. In addition to facilitating class F amplifier operation, the plurality of resonant circuits can also be implemented with other circuit elements to provide output impedance transformation in a way that facilitates efficient amplifier operation.

Abstract: A method of detecting a set up signal having a predetermined frequency and used for data transmissions over a communication network comprises comparing an energy level of a filtered received signal with a first predetermined value and providing a first detect signal, comparing an energy level of a component of the received signal at a predetermined frequency with a second predetermined value and providing a second detect signal. In addition, an autocorrelation function is performed on the received signal to discriminate between the set up signal and other signals in the received signal and a check signal is provided when the autocorrelation function identifies the set up signal. The set up signal in the received signal is detected in response to the first and the second detect signals and the check signal. A method of detecting phase reversals in the set up signal is also disclosed.

Abstract: A processor may efficiently implement register renaming and checkpoint repair even in instruction set architectures with large numbers of wide (bit-width) registers by (i) renaming all destination operand register targets, (ii) implementing free list and architectural-to-physical mapping table as a combined array storage with unitary (or common) read, write and checkpoint pointer indexing and (iiii) storing checkpoints as snapshots of the mapping table, rather than of actual register contents. In this way, uniformity (and timing simplicity) of the decode pipeline may be accentuated and architectural-to-physical mappings (or allocable mappings) may be efficiently shuttled between free-list, reorder buffer and mapping table stores in correspondence with instruction dispatch and completion as well as checkpoint creation, retirement and restoration.

Abstract: A power source delivers power from a main power source using switching by a normally on transistor. A driver switches on and off the normally on transistor under a control signal by a controller during regular operation. A housekeeping power supply delivers auxiliary power to the driver. The driver switches off the normally on transistor during irregular operation. Irregular operation occurs at least when the control signal is absent or no auxiliary power is available or during transients such a power up or down. Bridge block pairs thereof can be arranged to form a half bridge power switch, an H bridge switch, a three phase bridge switch, a multi-phase switch, a buck converter, a buck-boost converter, or a boost converter.

Abstract: A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body

Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling is presented. The semiconductor device has a substrate on which a first circuit and a second circuit with inputs and outputs are formed proximate to each other. An isolation structure of electrically conductive material is located between components of the first and second circuits, the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. The isolation structure may be positioned on or over exterior surfaces of the semiconductor device housing or inside the housing. In one embodiment, the isolation structure includes a first leg extending transverse to the surface of the substrate and a first cross member connected to and projecting from the first leg over the substrate.

Abstract: An apparatus comprising: at least one processor; and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform static code analysis of a plurality of instructions comprising, for each instruction: determining whether a trace message is generated by the instruction; determining whether a size of the trace message generated by the instruction is dependent on a context; determining a size of the trace message generated by the instruction; and updating the context; and to perform determining a cumulative size of trace messages generated by the plurality of instructions.