Abstract: A bit storage device, integrated circuit, and method are provided. The bit storage device comprises registers to store an actual value, an inverse value, a differential actual value, and a differential inverse value, a validation circuit including validation inputs coupled to outputs of the registers and including a validity output to provide a validity indication, and a write circuit including write circuit inputs coupled to the registers, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and either the second register to store the inverse value or the fourth register to store the differential inverse value, and, at a second clock edge, the third register to store the differential actual value and the other of the second register and the fourth register to store to store the inverse value or the differential inverse value, respectively.

Abstract: The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.

Abstract: A non-transitory machine-readable storage medium encoded with instructions for execution by a keyed encryption operation by a cryptographic system mapping an input message having an encoded portion and a padding portion to an output message, including: instructions for receiving a padding value k; instructions for receiving the input message, wherein the padding portion has a size indicated by the padding value k; instructions for computing a first portion of the encryption operation to produce a first portion output; instructions for computing a compensation factor corresponding to the padding portion of the input message; and instructions for compensating the first portion output based upon the compensation factor.

Abstract: A Doherty amplifier includes an output combining network that has a first combining network input coupled to a main amplifier path, a lowest-order combining network input coupled to a lowest-order peaking amplifier path, and N?2 additional combining network inputs coupled to other peaking amplifier paths. A final summing node is coupled to the combining network output, and is directly coupled to the first combining network input. N?2 intermediate summing nodes are coupled to the N?2 additional combining network inputs. An offset line is coupled between the lowest-order combining network input and a lowest-order summing node. A longest phase delay imparted by the output combining network on a peaking RF signal between the lowest-order combining network input and the final summing node is greater than all other phase delays imparted on any other RF signal provided to the first combining network input and the N?2 additional combining network inputs.

Abstract: This disclosure describes a network flow framework that generates customized network applications based upon user inputs that invokes various software building block functions to process ingress data packets. The network flow framework creates a network application pointer that points to the customized network application, and stores the network application pointer with application classification keys in a classification entry. When the network flow framework receives an ingress data packet, the network flow framework matches the ingress packet's classification key to the application classification key in the classification entry. As such, the network flow framework retrieves the network application pointer from the classification entry and stores the network application pointer in the ingress data packet's header. In turn, the network flow framework retrieves the customized network application corresponding to the network application pointer and processes the ingress data packet accordingly.

Abstract: Debug architecture for multithreaded processors. In some embodiments, a method includes, in response to receiving a halt command, saving a context of a thread being executed by a processor core to a context memory distinct from the processor core; suspending execution of the thread; and initiating a debug of the thread using the context stored in the context memory. In other embodiments, an integrated circuit includes a processor core; a context management circuit coupled to the core; and a debug support circuit coupled to the context management circuit, the debug support circuit configured to send a halt request to the context management circuit and the context management circuit configured to, in response to having received the request, facilitate a debug operation by causing execution of a thread running on the core to be suspended and saving a context of the thread into a context memory distinct from the core.

Abstract: A wireless charging system includes a power transmitting device and a power receiving device. In the transmitting device, a transmitting coil converts a drive signal from a drive signal circuit into an alternating magnetic field. In the receiving device, a receiving coil produces an alternating waveform from the magnetic field, and a rectifier rectifies the alternating waveform to deliver power having a rectified voltage. A modulation circuit causes a loading circuit to be coupled to and uncoupled from the receiving coil at a pre-determined modulation rate when, for example, the rectified voltage is greater than a threshold voltage. Back in the transmitting device, a modulation detector circuit detects modulation of the load impedance, and when the load impedance is modulating at the pre-determined modulation rate, causes the drive signal circuit to adjust a characteristic of the drive signal, resulting in an adjustment in an intensity of the magnetic field.

Abstract: A package includes a MEMS die and a cap element coupled to and stacked with the MEMS die. The MEMS die includes at least two physically isolated pressure sensors, each of which resides on its individual cantilevered platform structure. A first pressure sensor is vented to a first external environment via a first vent extending through the bottom of the MEMS die and is adapted to detect a first pressure of the first external environment. The MEMS die can be coupled to a lead frame having an opening that is aligned with the first vent. A second sensor is vented to a second external environment via a second vent extending through the cap element and is adapted to detect a second pressure of the second external environment. A difference between the first and second pressures is the differential pressure.

Abstract: A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.

Abstract: A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.

Abstract: Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

Abstract: The present disclosure provides embodiments for diodes, devices, and methods for polar vapor sensing. One embodiment of a diode includes a first electrode to which an electric field is applied; a second electrode to which the electric field is applied; and a vapor gap region between the first electrode and the second electrode. A total capacitance measured between the first electrode and the second electrode varies based on presence of a polar vapor species on at least a portion of an electrode surface of at least one of the first electrode and the second electrode.

Abstract: A device may include countermeasure circuitry that provides a countermeasure check that protects device logic. The device may also include enforcement circuitry that non-deterministically enforces the countermeasure check on the device logic so that the device logic is not always protected by a countermeasure action within the countermeasure check. The device may non-deterministically enforce the countermeasure check according to an enforcement rate, and the device may adjust the enforcement rate depending on a priority of the device logic or device logic portion protected by a particular countermeasure check.

Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.

Abstract: In general the embodiments described herein can provide alternating-current (AC) resonating filters. These resonating filters comprise a transmission line, a first resonator, and a second resonator. The first resonator is configured to block AC signals in a first frequency range, while the second resonator is configured to block AC signals in a second frequency range, where the second frequency range is higher than the first frequency range. The transmission line has a first node coupled to an AC source, and the first resonator is coupled to the transmission line a first distance from the first node, and the second resonator is coupled to the transmission line a second distance from the first node, where the second distance is greater than the first distance. When so configured the resonating filter can effectively block signals in multiple selected frequency bandwidths.

Abstract: A resistive non-volatile memory (NVMN) cell has three select transistors connected together in series. A first resistive element has a first terminal connected between first and second select transistors and a second terminal. A second resistive element has a first terminal connected between second and third transistors. In a first embodiment, the second terminals of the first and second resistive elements are connected to bit lines. In a second embodiment, the second terminals of the first and second resistive elements are connected to source lines. In the first embodiment, when the center select transistor is conductive, the first and second resistive elements become a resistor-divider. Each of the first and second resistive elements include a magnetic tunnel junction (MTJ).

Abstract: There is described a device for removing an offset from a signal, the device comprising (a) a frequency estimation unit (260) for estimating a frequency of the signal, (b) an offset estimation unit (222) for estimating the offset in the signal by applying an adaptive low pass filter to the signal, wherein a cut-off frequency of the adaptive low pass filter is determined based on the frequency of the signal estimated by the frequency estimation unit (260), and (c) a subtraction unit (230) adapted to subtract the offset estimated by the offset estimation unit (222) from the signal. There is also described a filter unit comprising the device. Furthermore, there is described a corresponding method of removing an offset from a signal as well as a computer program and a computer program product for performing the method by means of a computer.

Abstract: An electronic device comprises a controllable capacitor bank and a capacitive divider arranged in parallel with the capacitor bank and configured to linearize the capacitor bank in a linearization frequency range of a frequency characteristic of the electronic device. The capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank. A control circuit coupled to one or more control inputs of the capacitive divider and controllable capacitor bank is configured to modify the equivalent capacitance of the capacitive divider and the controllable capacitor bank for providing capacitance steps, each capacitance step being variable over frequency such that for each step a frequency change ?f of the frequency characteristic is maintained constant in the linearization frequency range.

Abstract: Generating a target layout of an integrated circuit includes providing a source layout comprising one or more source pcells having one or more shapes; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit; for each shape of each source pcell, determining a corresponding target shape having a contour composed of edges with defined lengths, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, determining a corresponding edge of the corresponding target shape; for each edge, defining an edge length constraint for constraining the edge to have the length of the edge of the corresponding target shape; applying a legalization procedure to the source layout based on the connectivity constraints, the target design constraints, and the edge length constraints.