Abstract: A semiconductor die comprising a terminal structure for an active power device. The terminal structure comprises a metallic layer arranged to be electrically coupled between the active power device and an external contact of an integrated circuit package, a conductive sub-structure extending in parallel with the metallic layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the metallic layer and a reference voltage plane, and interconnecting elements extending between the metallic layer and the conductive sub-structure and electrically coupling the metallic layer to the conductive sub-structure.

Abstract: A method and apparatus for an orthogonal frequency division multiplexed (OFDM) communication system for communication in the presence of cyclostationary noise is provided. A receiver receives from a medium a channel measurement packet of a communication channel. The channel measurement packet has a measured transmission characteristic. The measured transmission characteristic of the received channel measurement packet is compared to a defined transmission characteristic to provide a comparison. A modulation coding scheme (MCS) map referenced to a phase of a cyclostationary noise period of the medium is generated based upon the comparison. The MCS map is sent to a transmitter via the medium. Signals including packets that have been mapped to subcarriers based on the MCS map are received from the medium. Subcarriers of the signals received from the medium are demapped using the MCS map referenced to the phase of the cyclostationary noise period of the medium.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.

Abstract: A method of generating identification data for identifying software is disclosed. The method includes executing said software so as to alter one or more addresses of a memory stack reserved in memory for execution of the software. Identification data is then generated for identifying the software based on the one or more altered addresses of the memory stack.

Abstract: A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field effect transistor, a body drive stage to manufacture the body region of the power field effect transistor is shortened to obtain a relatively low on resistance for the power field effect transistor. Before the implanting stage of the dopants of the body region, a pre body drive stage is introduced. During the pre body drive stage and the body drive stage sidewalls of a polysilicon layer of the power field effect transistor are oxidized to obtain a power field effect transistor which has at the sidewalls an oxidized polysilicon layer that is thick enough to prevent a premature current injection from the gate to the source regions of the power field effect transistor.

Abstract: A voice coil motor displacement sensor and a voice coil motor controller that uses said sensor. The sensor configured to apply an alternating measurement signal at a predetermined frequency to a voice coil motor, the sensor configured to use a measure of a voltage across and a current through the voice coil motor to determine its impedance at the predetermined frequency and determine an estimated displacement of said voice coil motor using said impedance and a predetermined displacement-impedance function.

Abstract: A test method and system are provided for testing a switched mode power supply in open loop on an automated test equipment device by applying a low frequency waveform signal (209) to a compensator filter (225) and simultaneously capturing and processing the input (223) and output (222) to the compensator filter (225) to determine the phase difference therebetween.

Abstract: A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component.

Abstract: A method for determining the concentration of an analyte is provided. The method comprises: applying an alternating voltage to a first electrode and a second electrode of a sensor in the presence of the analyte; measuring a first capacitance of the sensor in presence of the analyte; irradiating the analyte for a predetermined time period at a discrete frequency within a predetermined frequency range; measuring a second capacitance of the sensor at an end of the predetermined time period; determining a difference between the first and second capacitances; and determining the concentration of the analyte based on the difference. Also, the method includes determining a composition of an analyte. The discrete frequency is associated with the difference to determine a frequency response. The frequency response is used to determine the composition of the analyte.

Abstract: In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.

Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.

Abstract: An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

Abstract: Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Abstract: Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

Abstract: A touch-screen interface circuit configured to operate in at least three modes comprises a first resistive x-plate having at least a first x-terminal connected in the first mode to a voltage supply and a second x-terminal connected in first mode to circuit ground; a voltage regulator circuit comprising a floating reference voltage source connected in first mode to the second x-terminal, and to a first input of a touch-screen reference buffer circuit having a second input connected in first mode to the first x-terminal; the voltage regulator circuit arranged to control in first mode a connection between the voltage supply and the first x-terminal; and a second resistive y-plate having at least a first y-terminal and being arranged to apply a wiper contact to the first x-plate, the wiper contact having an x-position, y-position and pressure.

Abstract: Various exemplary embodiments relate a system and method for supplying power. The system may include an input/output port, a regulator, and a clamp. The regulator may supply power to the input/output port in a first mode, sink current from the input/output port in a second mode, and be disabled in a third mode. The clamp may be disabled in the first and second modes, and may limit the voltage at the input/output port below a first value in the third mode.

Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.

Abstract: A method of performing a secure function on data inputs by a security module, including: receiving an encrypted data value by the security module; decrypting the encrypted data value using a white-box decryption block cipher and encoding the decrypted data value, wherein the data value is invisible to an attacker; performing a function on the encoded data value and producing an encoded result of the function, wherein the data value and the result are invisible to the attacker; decoding the encoded result of the programmed function and then encrypting the result using a white-box encryption block cipher, wherein the result is invisible to the attacker.

Abstract: An analog delay cell is provided that includes a transconductance-capacitance stage and an inductive transimpedance amplifier stage that provides an all-pass transfer function. In another embodiment, an adaptive analog delay cell including a transconductance (gm) plus capacitance (C) stage and an inductive-capacitance transimpedance amplifier (TIA) stage with digitally programmable phase-shift is provided. The adaptive analog delay cell increases the phase-shift by incorporating an LC network in the feedback path of the transimpedance stage. The disclosed analog delay cells can be used to provide delays in a tapped delay line. Also, the disclosed analog delay cells may be used to perform the multiplier and summation functions of a tapped delay line in addition to providing the delays. In another embodiment, the transimpedance amplifier stage includes an inductive-capacitive transimpedance amplifier stage.