Abstract: A processor may efficiently implement register renaming and checkpoint repair even in instruction set architectures with large numbers of wide (bit-width) registers by (i) renaming all destination operand register targets, (ii) implementing free list and architectural-to-physical mapping table as a combined array storage with unitary (or common) read, write and checkpoint pointer indexing and (iiii) storing checkpoints as snapshots of the mapping table, rather than of actual register contents. In this way, uniformity (and timing simplicity) of the decode pipeline may be accentuated and architectural-to-physical mappings (or allocable mappings) may be efficiently shuttled between free-list, reorder buffer and mapping table stores in correspondence with instruction dispatch and completion as well as checkpoint creation, retirement and restoration.

Abstract: A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.

Abstract: A real-time distributed network module arranged to provide an interface between at least one master application and at least one real-time distributed network. The real-time distributed network module comprises a first communications component arranged to transmit and receive real-time distributed network data over at least a first real-time distributed network connection, at least one further communications component arranged to transmit and receive real-time distributed network data over at least one further real-time distributed network connection at least one master application interface component arranged to provide an interface to the at least one master application, and at least one configuration component arranged to perform mapping of communication channels between the first communications component, the at least one further communications component and the at least one master application interface component.

Abstract: Various methods, apparatuses and systems are directed to battery-charging applications. As may be consistent with one or more embodiments discussed herein, a charging current for charging a battery is modulated, and the frequency of the modulated charging current is set based upon an impedance of the battery. Temperature of the battery is estimated based upon the impedance exhibited by the battery, while the battery is charged with the modulated charging current. In various implementations, the battery charging rate is controlled based on the estimated temperature.

Abstract: In one embodiment, a control system includes a first voltage domain circuit. The first voltage domain circuit includes circuitry for operating in a first voltage domain. The control system includes a second voltage domain circuit. The second voltage domain circuit includes circuitry for operating in a second voltage domain. The second voltage domain circuit includes a driver circuit. The driver circuit for providing a control terminal driving signal to make conductive a power switch. The second voltage domain circuit includes a replication circuit, the replication circuit having an output to provide a replicated signal of the control terminal driving signal. The control system includes a galvanic isolation barrier signal path between the first voltage domain circuit and the second voltage domain circuit. The replicated signal is provided by the second voltage domain circuit to the first voltage domain circuit via the galvanic isolation barrier signal path.

Abstract: A device for determining a rotor position in a polyphase electric motor having a first phase, a second phase and a third phase. A power control unit applies a first voltage on the first phase, and a second voltage on the second phase, the first voltage and the second voltage being periodic signals of opposite polarity, alternating between a first part and a second part of the alternating period, such as square waves. A sample unit samples a third voltage on the third phase for acquiring a first sample at a first instant in the first part and a second sample at a second instant in the second part, and a difference value between the first sample and the second sample. The difference value represents a mutual inductance between the stator coils due to the rotor position. A determination unit determines the rotor position based on the difference value.

Abstract: Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode.

Abstract: Operation of an insulated gate bipolar transistor (IGBT) is monitored by an apparatus that has a capacitor connected between a collector of the IGBT and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. The processing circuit also employs the capacitor current to provide an output voltage that indicates the voltage at the IGBT collector.

Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Abstract: A processing apparatus, comprising at least a first processing unit and a second processing unit, is proposed. The first processing unit comprises a set of first stateful elements, the second processing unit comprises a set of second stateful elements. A set of synchronization data lines may connect the first stateful elements to the second stateful elements in a pairwise manner. A control unit may control the first processing unit, the second processing unit and the synchronization data lines so as to copy the states of the first stateful elements in parallel via the synchronization data lines to the second stateful elements in response to a synchronization request. A method of synchronizing the processing units is also proposed.

Abstract: An embodiment of a microelectromechanical systems (MEMS) device is provided, which includes a substrate; a proof mass positioned in space above a surface of the substrate, wherein the proof mass is configured to pivot on a rotational axis parallel to the substrate; an anchor structure that includes two or more separated anchors mounted to the surface of the substrate, wherein the anchor structure is aligned with the rotational axis; and an isolation sub-frame structure that surrounds the anchor structure and is flexibly connected to each of the two or more separated anchors of the anchor structure, where the proof mass is flexibly connected to the isolation sub-frame structure.

Abstract: A current-to-voltage converter receives a current which varies with temperature according to a selected one of two or more temperature coefficient factors and converts it to a temperature-dependent voltage to be used as a control signal to a varactor in a voltage controlled oscillator, VCO, to compensate for temperature-induced frequency drift in the VCO. A feedback arrangement with hysteresis is provided for controlling the selection of the temperature coefficient factor and operates by comparing the temperature-dependent voltage with a reference voltage. The reference voltage may be pre-set and equivalent to a known operating temperature. A switching signal is generated when Vout approaches the reference voltage and in response, a control module generates a selection signal for selecting a different temperature coefficient factor.

Abstract: A sensor package includes a magnetic field sensor, where the magnetic field sensor includes an in-plane sense element and a flux guide configured to direct a magnetic field oriented perpendicular to a plane of the magnetic field sensor into the plane. A current carrying structure is positioned proximate the flux guide and circuitry is coupled to the current carrying structure. The current carrying structure includes a continuous coil having multiple substantially parallel conductive segments connected by additional conductive segments oriented Perpendicular to the parallel conductive segments to form a continuous series of loops. The circuitry is configured to provide an electric current to the continuous coil such that the electric current flows through each of the parallel conductive segments, wherein the electric current generates a magnetic field, and the magnetic field is applied to the flux guide to recondition a magnetic polarization of the flux guide.

Abstract: An equalizer circuit of a particular equalization stage of a equalizer circuit is omitted, and input signals that would have otherwise been received at the omitted equalization circuit bypass the equalization stage and are instead processed at an equalizer circuit included at the next stage. Thus, a subset of the received frequency-domain signals can be processed by equalizer circuits at a first stage, while the remaining received frequency-domain signals bypass the first stage and are processed at an equalizer circuit included at a second stage.

Abstract: A bit storage device, integrated circuit, and method are provided. The bit storage device comprises registers to store an actual value, an inverse value, a differential actual value, and a differential inverse value, a validation circuit including validation inputs coupled to outputs of the registers and including a validity output to provide a validity indication, and a write circuit including write circuit inputs coupled to the registers, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and either the second register to store the inverse value or the fourth register to store the differential inverse value, and, at a second clock edge, the third register to store the differential actual value and the other of the second register and the fourth register to store to store the inverse value or the differential inverse value, respectively.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an LDMOS transistor) is disposed in the semiconductor substrate at the surface. The device further includes a drift region of a second, opposite conductivity type disposed in the semiconductor substrate at the surface. The drift region extends laterally from the current carrying region to the gate structure. The device further includes a buried region of the second conductivity type disposed in the semiconductor substrate below the current carrying region. The buried region is vertically aligned with the current carrying region, and a portion of the semiconductor substrate with the first conductivity type is present between the buried region and the current carrying region.

Abstract: A method of making a microelectromechanical systems (MEMS) device includes etching away a sacrificial material layer to release a mechanical element of the MEMS device. The MEMS device is formed at least partially on the sacrificial material layer, and the etching leaves a residue in proximity to the mechanical element. The residue is exposed to an anhydrous solution to remove the residue. The residue may be an ammonium fluorosilicate-based residue, and the anhydrous solution may include acetic acid, isopropyl alcohol, acetone, or any anhydrous solution that can effectively dissolve the ammonium fluorosilicate-based residue.

Abstract: An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).

Abstract: A non-transitory machine-readable storage medium encoded with instructions for execution by a keyed encryption operation by a cryptographic system mapping an input message having an encoded portion and a padding portion to an output message, including: instructions for receiving a padding value k; instructions for receiving the input message, wherein the padding portion has a size indicated by the padding value k; instructions for computing a first portion of the encryption operation to produce a first portion output; instructions for computing a compensation factor corresponding to the padding portion of the input message; and instructions for compensating the first portion output based upon the compensation factor.

Abstract: A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.