Abstract: A method for altering execution of a program on a computer. The program resides in a memory unit that has a logical address space assigned thereto. The method comprises: operating the computer to start executing the program; operating the computer to suspend execution of the program; selecting a patch insertion address within a logical address range of the program, saving the original code residing at the patch insertion address; generating a patch routine; writing a jump instruction to the patch insertion address, thus overwriting said original code, wherein the jump instruction is arranged to instruct the computer to jump to a start address of the patch routine; and operating the computer to resume execution of the program. The patch routine is arranged to prompt the computer to: save a current context of the program; execute a user code; restore the saved context of the program; and execute a surrogate code.

Abstract: An OFDM receiving apparatus is provided for estimating a signal-to-noise ratio of a code-division multiplexed sounding signal transmitted over a wide channel of a wireless communication system. The apparatus separately determines the noise power level and the signal power associated with the sounding signal. Namely, the noise power level is determined in the frequency domain based on a noise covariance matrix. Further, the sounding signal's power level is determined, in the time domain, based on power delay profile of the wide channel over which the sounding signal has been transmitted.

Abstract: Various aspects of the present disclosure involve communications, and more specifically wireless communications with modulation. As may be implemented in accordance with one or more embodiments, a rectifier having a plurality of active circuits operates in first and second modes to modulate signals communicated via an antenna as follows. The first mode is at least a half-active mode in which at least one of the active circuits passes the signal, and the second mode consumes less power than the first mode. A modulator modulates a waveform of the signal by selectively operating at least one of the plurality of active circuits, therein setting an impedance of the rectifier and modulating an amplitude of the signal.

Abstract: A first-in first-out (FIFO) buffer system includes FIFO control logic and first and second storage partitions. Each storage partition includes a corresponding single-port memory bank and a prefetch buffer. The FIFO control logic alternates processing of PUSH commands between the first and second storage partitions. Additionally, the FIFO control logic anticipates POP commands based on the FIFO order and the alternating PUSH arrangement by initiating prefetches of data so that data to be accessed by a POP command is available at either the prefetch buffer (if the prefetch has completed) or the output of the single-port memory bank (if the prefetch has not yet completed) of the corresponding storage partition at the time the POP command is received, thereby enabling the output of the data for the POP command in the same clock cycle in which the POP command is received.

Abstract: Debugger system, method and computer program product for debugging instructions.

Abstract: A method of manufacturing a packaged semiconductor device includes patterning and plating silver nanoparticles in bonding areas of a lead frame, forming a hydrophilic group while oxidizing the silver nanoparticles, forming wire bonds on the silver nanoparticles, and encapsulating the wire bonds and the silver nanoparticles.

Abstract: A multi-rate cascaded continuous-time analog-to-digital converter has a plurality of sigma-delta modulator stages and includes first and second continuous-time sigma-delta modulators, and a summation element. The first continuous-time sigma-delta modulator operates at a first sampling rate. The second continuous-time sigma-delta modulator operates at a second sampling rate higher than the first sampling rate. The second continuous-time sigma-delta modulator has a continuous-time voltage controlled oscillator (VCO) quantizer, and a feedback loop coupled between the input and the output. The second continuous-time sigma-delta modulator is cascaded with the first continuous-time sigma-delta modulator. The summation element has inputs coupled to outputs of the first and second continuous-time sigma-delta modulators.

Abstract: A multi-wafer structure is formed by forming a cavity in a cap wafer and forming a first seal material around the cavity. A collapsible standoff structure is formed around the cavity. A movable mass is formed in a device wafer. A second seal material is formed around the movable mass. The first seal material and the second seal material are of materials that are able to form a eutectic bond at a eutectic temperature. The cap wafer and the device wafer are arranged so that the first and second seals are aligned but separated by the collapsible standoff structure. Gas is evacuated from the cavity at a temperature above the eutectic temperature using a low pressure. The temperature is lowered, the cap and device wafer are pressed together, and the temperature is raised above the eutectic temperature to form a eutectic bond with the first and second seal materials.

Abstract: There is described a device (100) for communicating with RFID-tags, the device (100) comprising (a) an antenna unit comprising a first antenna (110; 200) and a second antenna (120; 200), and (b) a controller (130) connected to the antenna unit. The controller (130) is adapted to sequentially feed different polling signals to the antenna unit such that corresponding signals are individually and simultaneously radiated by each of the first antenna (110; 200) and second antenna (120; 200). There is also described a home appliance comprising the aforementioned device (100). Furthermore, there is described a method for communicating with RFID-tags by an antenna unit comprising a first antenna (110; 200) and a second antenna (120; 200). The described method comprises sequentially feeding different polling signals to the antenna unit such that corresponding signals are individually radiated by each of the first antenna (110; 200) and second antenna (120; 200).

Abstract: A data processor includes a packet selector. The packet selector creates an ordered list of packets, each packet corresponding to a respective communication flow, determines whether each packet in the ordered list of packets is eligible for transfer to a prefetch unit based on whether a preceding packet in the same communication flow has been transferred to the prefetch unit, and sets a selection priority for each packet based on start time constraints for the respective communication flow, and based on a processing status of a preceding packet in the communication flow.

Abstract: A Doherty amplifier device operable over multiple frequency bands includes a controller that, in some embodiments, is configured to output a carrier bias signal to a first amplifier and a peaking bias signal to a second amplifier as part of a first operating configuration associated with a first frequency band, and output the peaking bias signal to the second amplifier and the carrier bias signal to a third amplifier as part of a second operating configuration associated with a second frequency band. In some embodiments, the controller is configured to select an impedance inverter configuration associated with a respective frequency band. At least one impedance inverter configuration includes a compound impedance inverter including two or more impedance inverters coupled in series with at least one node between the two or more impedance inverters coupled to an output of a third amplifier.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Abstract: A joint user detection apparatus for a wireless communication system, such as OFDM systems, arranged to account for timing impairments experienced by CAZAC codes. The proposed apparatus brings improvements over conventional receiving apparatuses by allowing joint user channel estimation processing and joint user equalization processing while considering timing impairments of user associated information present within a symbol of a received signal. The proposed solution could be used on conventional receiving apparatuses since both joint user channel estimation processing and joint user equalization processing can be activated independently such that either one or both improvements may be activated as needed or as required by the design of the conventional receiving apparatuses. A method and a computer program are also claimed.

Abstract: The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.

Abstract: A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of the directed spanning tree includes processing circuitry to provide a coherency response in response to a snoop request. Each processing unit which is not a root or leaf of the directed spanning tree includes switch point circuitry having one or more ingress ports coupled to neighboring processing units in accordance with the directed spanning tree. The switch point circuitry includes a coherency tracking table configured to store a combined coherency response in response to a particular snoop request based on one or more coherency responses received at the one or more ingress ports from the neighboring processing units.

Abstract: Disclosed is an integrated circuit, system or architecture suitable for NFC functionality and including an NFC companion block connectible to a power source and capable to providing a non-continuous power boost to NFC signals, inter alia, thereby facilitating use of a broader range of antennas, multiple antennas, and thereby providing greater NFC functionality and versatility Further disclosed is a detachable antenna embedded in a potentially detachable shell which closely fits a mobile device and is adapted for use with the above mentioned integrated circuit, system or architecture.

Abstract: An electronic device is for controlling motor drive circuits for driving a multi-phase motor in a force assisted system. Each motor drive circuit selectively permitting current to flow into or out of a respective phase of the multi-phase motor connected to the motor drive circuit in response to being driven by respective control signals. A motor control circuit generates the control signals. A fault processor detects at least one fault condition causing a fault current in a first motor drive circuit. In the event of the fault condition being detected, at least one alternative control signal is generated for at least one motor drive circuit for permitting at least one compensation current to flow for reducing a faulty force due to the fault current.

Abstract: An apparatus for facilitating the re-distribution of processing load between a plurality of radio equipment controllers arranged in a daisy chain configuration on a Common Public Radio Interface. The apparatus may be included in each REC and has two framers which may co-operate to forward IQ data of antenna carriers received on a downlink from a preceding REC to a subsequent REC in the chain and a DMA module or channel which can read IQ data from a system memory for onward transmission. In a re-allocation mode, the framer may be reconfigured so that an AxC initially allocated to a preceding REC for processing may be instead, accessed by a second (usually redundant) transmit DMA module included in the apparatus from system memory and transferred to the framer for onward transmission.

Abstract: Embodiments of a control device for an electronic fuse and a method for controlling an electronic fuse are described. Embodiments of a control device for an electronic fuse may include an interface configured to receive a current from a transistor device of the electronic fuse. Additionally, the control device may further include a sense-and-control device coupled to the interface and configured to detect an increase in the current received at the interface under a standby mode of the electronic fuse and to output an interrupt signal in response to the increase in the current received at the interface.

Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves in response to receiving bits of an arbitration field of a CAN data frame at the CAN device, selecting a timing engine from a plurality of timing engines and sampling subsequent bits of the CAN data frame using the selected timing engine. The timing engines have different sample clock frequencies.