Abstract: A voltage regulator comprises a ground node, a pick-off node, a regulator branch, a load branch, and a current mirror the regulator branch and the load branch are connected in parallel between the pick-off node and the ground node; the load branch comprises one or more resistive connecting lines that are connectable in series with the load to generate a load current through the load branch; the regulator branch comprises a bias node, a resistive element, and a tap node; the bias node is arranged to provide a regulated bias voltage; the resistive element is connected between the bias node and the pick-off node; and the tap node is connected between the bias node and the resistive element. The current mirror is connected to the tap node and arranged to draw a mirror current from the tap node; the mirror current having a component that is proportional to the load current.

Abstract: Processing logic circuit has State Retention Power Gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.

Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

Abstract: A CMOS device comprises a substrate with a plurality of regions, the regions including an N-type region and a P-type region which meet each other in a PN-boundary, two or more P-type active regions embedded in the N-type region, and two or more N-type active regions embedded in the P-type region. The PN-boundary or a section of the PN-boundary is a chain of line segments. Any two adjoining line segments of the chain are angled relative to each other at their connecting point. The CMOS device can be designed using abutting standard cells. For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.

Abstract: A spread-spectrum clock generation circuit comprises at least one comparison element; at least one charge storage device arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a first oscillation frequency of the spread-spectrum clock generation circuit; and a switched charge storage arrangement additionally arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a second oscillation frequency of the spread-spectrum clock generation circuit.

Abstract: A voltage recovery circuit in an integrated circuit is provided. The voltage recovery circuit includes a bootstrap circuit coupled to a cascode switch circuit. The bootstrap circuit includes a first transistor coupled in series to a second transistor, a resistive element is coupled between the second transistor and an output of the voltage recovery circuit, and a capacitive element is coupled between control electrodes of the first and second transistors and the output. The cascode switch circuit includes a third and fourth transistor coupled in series. The third transistor includes a current electrode coupled to receive a first input voltage, and a control electrode coupled to the control electrodes of the first and second transistors. The fourth transistor includes a current electrode coupled to the output, and a control electrode coupled to a current electrode of the second transistor and a terminal of the resistive element.

Abstract: A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output. The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the plurality of LUTs; and generate an output signal, y[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element.

Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.

Abstract: An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.

Abstract: The present disclosure provides for a method and semiconductor device for low power configuration. In one embodiment, a method includes receiving a packet from a host device, where the packet is received at a USB (Universal Serial Bus) device. The method also includes detecting, by the USB device, that the packet includes an endpoint address of a low power endpoint. The method also includes entering a low power mode state, in response to the detecting, where the USB device includes a USB clock domain that includes an internal reference clock (IRC) and clock recovery logic, and a clock tree block located outside of the USB clock domain. The entering the low power mode state includes disabling the clock tree block, and clocking the USB clock domain using the IRC and clock recovery logic.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: The embodiments described herein provide compensation for mutual inductance in a multi-path device. In one embodiment, a device includes a multi-path integrated device. The multi-path integrated device includes a first output and a second output. The first output is configured to be coupled to a first output lead through a first bonding wire, and the second output is configured to be coupled to a second output lead through a second bonding wire. Due to their proximity, the second bonding wire has a first mutual inductance with the first bonding wire. A first compensation network is coupled to the first output, and a second compensation network is coupled to the second output. The second compensation network is configured to have a second mutual inductance with the first compensation network. The second mutual inductance at least partially cancels the effects of the first mutual inductance.

Abstract: An ESD protection device for shunting an electrostatic discharge current from a first node to a second node, and an integrated circuit including the same. The device includes a first bipolar transistor having a collector and an emitter located in a first n-type region. The emitter of the first transistor is connected to the first node. The device also includes a second bipolar transistor having a collector and an emitter located in a second n-type region. The emitter of the second transistor is connected to the collector of the first bipolar transistor. The device further includes a pn junction diode including a p-type region located in a third n-type region. The p-type region of the diode is connected to the collector of the second bipolar transistor and the third n-type region is connected to the second node.

Abstract: A method and a computer program product for disassembling a mixed machine code are described. The machine code is provided as a sequence of code items including one or more instructions and one or more data items. The method comprises: storing the sequence of code items in accordance with a corresponding sequence of addresses; executing the machine code, thereby generating an execution trace; and partitioning the sequence of addresses into instruction address blocks and data address blocks on the basis of control data, the control data comprising at least the execution trace.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: A device for determining a rotor position in a polyphase electric motor has a power control unit for applying drive voltages according to a pulse width modulation scheme so as to synchronously drive the motor. A measurement unit is arranged for measuring a voltage value on a respective phase by determining a zero-crossing interval where the phase current is around zero, disconnecting the phase from the respective drive voltage during the zero-crossing interval, and measuring the voltage value when the drive voltage of a first other phase is the supply voltage and the drive voltage of a second other phase is the zero voltage. A position unit is arranged for determining the rotor position based on the voltage value.

Abstract: Mobile devices such as mobile phones include amplifiers for example audio and RF amplifiers which may consume a significant amount of the available power supplied by a battery. An amplifying system 100 for a mobile device is described the amplifying system comprising a current monitor 12 arranged between a first supply node and a second supply node and operable to monitor a current flow between the first and second supply nodes and to output a monitored current value; a peak current limiter 14 configured to limit an amplifier current to an amplifier to not exceed a maximum peak current value and coupled to a one of the first supply node and the second supply node; a controller coupled to the current monitor output and configured to control the peak current limiter. The amplifying system can dynamically manage the peak current available to the amplifier dependent on the load current being supplied by a battery.

Abstract: Data packets are received from a plurality of communication nodes within a local Ethernet network, the data packets including a media access control address (“MAC address”) are indicative of a destination and a data packet traffic class. Based upon the traffic class of each data packet, each of the received data packets are assigned in to one of the plurality of queues of a memory circuit. Based upon the MAC address of each data packet, the data packets within at least one of the queues are sorted. Each queue is then serviced and the data packets within are transmitted based upon the sorting.

Abstract: A method of charging a mobile device on a charge pad. The method includes receiving a wireless charge from at least one of a plurality of charge pad power coils. The method also includes enabling communications between the charge pad and the mobile device. The method also includes sending a command from the wireless device to the charge pad to adjust a characteristic of the wireless charge at the charge pad and to enable the wireless device to control the characteristic of the wireless charge of the charge pad.

Abstract: In an embodiment, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes a load modulation module, a current source coupled to the load modulation module, an interface to a resonant circuit, the interface coupled to the load modulation module and the current source, and an interface to a charge source, the interface coupled to the current source, wherein the load modulation module is configured to provide a signal for transmission by modifying the load through the load modulation module, and wherein the current source is configured to provide a signal for transmission by generating pulses of current.