Abstract: The invention relates to a CMOS device (10) with an NMOST I and PMOST 2 having gate regions (1D,2D) comprising a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and both comprise as the further element an element selected from the group comprising carbon, oxygen and the chalcogenides. Preferably both the first and second conducting material comprise a compound of molybdenum and carbon or oxygen. The invention also provides an attractive method of manufacturing such a device.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: The invention relates to a method comprising the steps of: a first network device (DEVI) outputting content (CONT), the first network device (DEVI) retrieving an address (ADDR2) of a second network device (DEV2) from a third device (DEV3), and the first network device (DEVI) transmitting said content (CONT), which was output at the time of retrieving said address (ADDR2), to said second network device (DEV2). Furthermore, the invention relates to a network device (DEVI), comprising: means for outputting content (CONT), means for retrieving an address (ADDR2) of a second network device (DEV2) from a third device (DEV3), and means for transmitting said content (CONT), which was output at the time of retrieving said address (ADDR2), to said second network device (DEV2).

Abstract: Artifacts occur in the images rendered on a 100 Hz TV as a result of the vertical and horizontal blanking intervals. These intervals cause transitions between high activity and low activity of the TV's digital processing parts which in return cause disturbances on the power supply lines. By keeping the digital processing parts active during the blanking intervals, the artifacts are removed.

Abstract: A micro fluidic chip (100) for handling fluidic droplets (101), the micro fluidic chip (100) comprising a plurality of electrodes (103) being arranged in a Back End of the Line portion (104) of the microfluidic chip (100), and a control unit (106) adapted for controlling electric potentials of the plurality of electrodes (103) to generate electric forces for moving the fluidic droplets (101) along a predefined trajectory.

Abstract: A system comprises a plurality of electronic devices connected to a bus in operational use. For automatic address configuration of the devices, the devices are daisy-chained. In the daisy-chain, a preceding one of the devices transfers its address to a next one of the devices, and the latter determines its own address via an offset with respect to the address received.

Abstract: The present invention relates to a ferroelectric varactor (400) that comprises a dielectric-layer stack (408) between electrodes (406, 410). The dielectric-layer stack comprises an alternating layer sequence of at least three dielectric layers. At cc least two first dielectric layers of the dielectric-layer stack are made of a non-single-crystalline first dielectric material having a first dielectric constant, at least one second dielectric layer of the dielectric-layer stack is made of a non-single-crystalline second dielectric material with a second dielectric constant that differs from the first dielectric constant. One of the first and second dielectric materials exhibits a weaker ferroelectric hysteresis. The dielectric material with the weaker ferroelectric hysteresis makes up more than 20% of the total volume of the dielectric-layer stack.

Abstract: A LED string is divided into segments that each have a bypass-switch and a driver for the bypass-switch. The driver is powered by a supply voltage locally generated from the forward-voltages of the LEDs of the segment.

Abstract: A driver (DR) for a brushless motor comprises at least three outputs (OU, OV, OW) for supplying coils (U, V, W) of the motor. The driver (DR) has a first and a second output (OU, OV) for providing a first and a second supply signal (SU, SV) respectively. During a first commutation state (CS1) the first and the second supply signal (SU, SV) respectively have a first and a second average voltage (V1, V2). During a second commutation state (CS2) succeeding the first commutation state (CS1) the first and the second supply signal (SU,SV) respectively have a third and a fourth average voltage (V3, V4). The second and the third average voltage (V2, V3) having a value intermediate the first average voltage (V1) and the fourth average voltage (V4).

Abstract: A UWB or other transmitter reduces interference to a narrow-band victim receiver on a periodic basis by means of a frequency swept notch. The notch may be created using active interference cancellation signal processing or simple deletion of sub-carriers. Details are given of both methods.

Abstract: A MEMS tunable capacitor comprises first and second opposing capacitor electrodes (10,12), wherein the second capacitor electrode (12) is movable by a MEMS switch to vary the capacitor dielectric spacing, and thereby tune the capacitance. A tunable dielectric material (14) and a non-tunable dielectric material are in series between the first and second electrodes. The tunable dielectric material occupies a dimension gd of the electrode spacing, and the non-tunable dielectric material occupies a dimension g of the electrode spacing. A third electrode (20) faces the movable second electrode (12) for electrically controlling tunable dielectric material.

Abstract: An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate (103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104), an extended drain (106) implanted in a surface portion of the substrate (101) adjacent the second side wall (105) of the gate (103), a spacer (107) on the second side wall (105) of the gate (103), a source (108) implanted in a surface portion of the substrate (101) adjacent the first side wall (104) of the gate (103), and a drain (109) implanted in a surface portion of the substrate (101) adjacent the spacer (107) in such a manner that the extended drain (106) is arranged between the gate (103) and the drain (109).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).

Abstract: An integrated circuit (100) is disclosed comprising a plurality of circuit portions (130), each of the circuit portions having an internal supply rail (170) coupled to a global supply rail (160) via a cluster (140) of switches (152; 154) coupled in parallel between the internal supply rail (170) and the global supply rail (160). Each cluster (140) of switches (152; 154) has a first switch (152) having a first size and a second switch (154) having a second size, a fault-free first switch (152) having a higher resistance than a fault-free second switch (154). The IC (100) further comprises a test arrangement for testing the respective clusters (140) of switches (152; 154) in a test mode. The test arrangement comprises a test control input; a test output coupled to the respective internal supply rails (170) and control means (110, 114, 116) coupled to the test control input for enabling a selected cluster (140) of switches (152; 154) in the test mode.

Abstract: A digital controller for low-power DC-DC switch mode power supplies (SMPS) suitable for on-chip implementation and use in portable battery-powered systems is provided. The digital controller allows operation at ultra high constant switching frequencies and can be implemented with a simple low-power digital hardware. The digital controller includes a digital pulse width modulator (DPWM), based on a multibit 2nd orders sigma-delta (?-?) principle, and a dual-sampling mode PID compensator. The output voltage is either sampled at a frequency lower than the switching frequency (undersampled) or sampled at the switching rate. In steady-state, undersampling results in reduced power consumption, while during transients, sampling at the switching rate provides fast transient response. Another aspect of the present invention is a dual sampling/clocking scheme, which is relied on by the DPWM described.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate latched service requests. Methods for one or more slave devices to request service from a master device involve detecting a condition that asserts a request for service signal, at a common node independent from the serial data transfer bus, to a master device of the bus. The request for service is latched it, within the slave, such that the request for service remains asserted regardless of a change in the detected condition. The request for service is de-asserted in response to interrogation of the slave, using the serial data transfer bus, by the master device. Devices may be configured as general purpose Input/Output devices, CODEC arrangements, or other slave devices, and may conform to I2C and/or SMBus serial communication specifications.

Abstract: In order to provide a security system (100; 100?) for securing the integrity of at least one arrangement comprising multiple devices (10, 12; 10a, 12a, 12b, 12c), for example of at least one network and/or of at least one computer system, wherein manipulation of the arrangement comprising these multiple components or devices (10, 12; 10a, 12a, 12b, 12c) is prevented, it is proposed that the devices (10, 12; 10a, 12a, 12b, 12c) communicate with each other, in particular by exchanging messages (20) between and among each other, that each device (10, 12; 10a, 12a, 12b, 12c) comprises at least one respective security unit (30, 32) [a] for performing at least one authentication by means of exchanged messages (20) and [b.i] in case of a valid authentication for enabling operation of the respective device (10; 10a) and/or of at least one of the other devices (12; 12a, 12b, 12c) and [b.

Abstract: A pulse width modulation (PWM) circuit comprises a first integrator (g m1) with a first feedback capacitor (C1), a second integrator (gml) with a second feedback capacitor (C2) and a comparator (A0) having a first input (V1) connected to the output of the first integrator (gm1) and a second input (V2) connected to the output of the second integrator (gm2). A connection path comprising a resistor (R2) is established from the output of the first integrator (gm1) to an input of the second integrator (gm2). The first and second feedback capacitors (C1, C2) have capacities with a non-linear factor X(V) and a circuit with an inversely non-linear factor X?1(V) is arranged in the connection path between the output of the first integrator (gm1) and said input of the second integrator (gm2). The PWM circuit may form path of a Class-D amplifier.

Abstract: A method (100) is disclosed for determining the behaviour of an integrated circuit comprising a plurality of resources and being configured to execute a plurality of operations that each require temporary allocation and deallocation of at least a subset of the plurality of resources during said execution. The method comprises the steps of monitoring (130) the execution of at least some of the plurality of operations during an execution run of the IC, capturing (140) events indicating the (de)allocation of resources during said execution, capturing events (150) indicating an operational relationship between allocated resources during said execution, assigning (140, 150) a time stamp to each event; and making (160) the captured events available for visualization. This facilitates the visualization of events that are interrelated in terms of the operation to which they are assigned at a given time instant.

Abstract: A current-steered DAC has first and second differential outputs for providing an analog output signal under control of a digital input signal. In operational use of the DAC, the output signal has a differential component, which is representative of the digital input signal, and also has a first common-mode component. The DAC has circuitry operative to add an extra common-mode component to both the first and second differential outputs so as to make a sum of the first common-mode component and the extra common-mode component substantially independent of a state change of the digital input signal.