Abstract: An embedded DRAM memory device comprising one or more cylinder type cell capacitors. Contact pillars (25) are provided in a PMD layer (27) on a substrate (10), and the lower (or storage mode) electrodes of the capacitors are formed by depositing an end stop layer (40) over the contact pillars (25) and then forming second contact trenches (62) in an oxide layer (60) provided over the PMD layer (27). The second contact trenches (62) are aligned with respective contact pillars (25) and filled with, for example, a barrier material plus tungsten. The oxide layer (60) is selectively etched at the location of the contact trench (62) to the end stop layer (40). The end stop layer etched and the PMD layer (27) is subsequently etched along a portion of the length of the first contact pillar (25) to form a trench (62). Finally, the tungsten in the second contact trench (62) is selectively etched through the barrier layer, so as to leave a barrier layer (64) e.

Abstract: A circuit arrangement for supporting and monitoring a microcontroller, which is constructed externally of the microcontroller, comprises a watchdog circuit for monitoring the microcontroller, which circuit outputs an error signal if not reset by the microcontroller within a watchdog period, and an interrupt circuit, which feeds important system messages to the microcontroller as interrupt events for processing. In order correctly to combine interrupt processing and watchdog operation, the watchdog circuit is connected to the interrupt circuit and cooperates therewith in such a way that the interrupt circuit feeds at most a predetermined number of interrupt events to the microcontroller within a watchdog period.

Abstract: A data processing device has a memory with writeable and erasable locations, such as a flash memory. The memory locations are store WOM codewords (Write Once Memory codewords in which successive generations of data can be encoded by setting bits from zero to one only). A data encoder encodes a received data value in a new codeword from the WOM code, as a function of the received data value and a previous codeword stored in the currently selected location. When the WOM codeword is exhausted the data encoder selects a new currently selected location from a logical series of locations and stores the new codeword in the new currently selected location. When all locations are exhausted a reset circuit resets a content of the locations in the logical series. On reading the currently selected location is read and decoded.

Abstract: The present invention relates to a write controller for a memory with a plurality of non-volatile storage cells, a read controller for a memory with a plurality of nonvolatile storage cells, to a combined write/read controller, to a solid state device comprising a memory with a plurality of non-volatile storage cells, a programmer device for writing a binary code to a non-volatile memory, to a method for writing data comprising at least one input bit to a memory having non-volatile storage cells, and to a method for controlling the integrity of data comprising at least one input bit stored in non-volatile storage cells of a memory. The basic concept of the present invention is to extend information stored in a non-volatile memory by at least one checking bit. The checking bit is allocated to one code bit, or to each of a plurality of code bits.

Abstract: Circuit arrangement for shifting the phase of an input signal, which circuit arrangement consists of two branches whose two output signals are 90° phase-shifted, and use of this phase shifter in a circuit arrangement for suppressing the mirror frequency. The filter systems in the two branches of the phase shifter are implemented in such a way that the phase difference between these two branches is 90°, independent of the frequency of the input signal. In the mirror frequency circuit, a frequency band is amplified or blanked during transmission. The base frequency BF constitutes the center of the frequency band. The amplitude difference is small in the solutions according to the invention. The amplitude difference is improved when the two 90° phase-shifted signals are matched or substantially equalized as regards their amplitude. The matching is performed in that the two signals are rectified and subsequently subtracted from each other.

Abstract: A monolithically integrated punch-through diode with a Schottky-like behavior. This is achieved as a Schottky-metal area (16) is deposited onto at least part of the first p-doped well's (9) surface. The Schottky-metal area (16) and the p-doped well (9) form the metal-semiconductor-transition of a Schottky-diode. The overvoltage protection of the inventive PT-diode is improved as the forward characteristic has a voltage drop that is less than 0.5V.

Abstract: A computer graphics processor is described comprising a model information providing unit (210) for providing information representing a set of graphics primitives, a rasterizer (227) capable of generating a first sequence of coordinates which coincide with a base grid associated with the primitive, a color generator (235) for assigning a color to said first sequence of coordinates, and a display space resampler (245) for resampling the color assigned by the color generator in the base grid for coordinates u,v to a representation in a grid associated with a display with coordinates x,y, in a first and a second transformation. The transformation is carried out in a first and a second pass, and optionally includes a transposition. The order of the passes and the decision to apply a transposition or not is based on an evaluation of the partial derivatives formula (I) two of which determine shear and two of which determine scaling in the transformations.

Abstract: The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200).

Abstract: The semiconductor device (11) of the invention comprises a circuit covered by a passivation structure (50). It is provided with a first and a second security element (12A, 12B) which comprise local areas of the passivation structure (50), and with a first and a second electrode (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which impedances differ. This is realized in that the passivation structure has an effective dielectric constant that varies laterally over the circuit. Actual values of the impedances are measured by measuring means and transferred to an access device by transferring means. The access device comprises or has access to a central database device for storing the impedances. The access device furthermore may compare the actual values with the stored values of the impedances in order to check the authenticity or the identity of the semiconductor device.

Abstract: A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made.

Abstract: An antenna device (AD) for a RF communication equipment, comprises i) a substrate (S) comprising front (FS) and back (BS) sides, ii) a planar antenna element (AE) fixed to the substrate back side (BS), iii) a group of at least one component (G1) fixed to the substrate front side (FS), in an area located under the antenna element (AE), and connected to the antenna element (AE) through at least a first connecting means (VH 1) passing through the substrate (S), and a low resistivity layer (BL) buried into the substrate (S) for connecting to ground in order to isolate at least the group of component(s) from electromagnetic disturbances induced by the antenna element (AE).

Abstract: At microwave frequencies, the use of transmission lines as a design element becomes interesting due to the small wavelengths. Inductors as part of an on-chip resonator can be made with a shorted stub, which is a transmission line, shorted at the end. Placing a MIM-capacitor at the beginning of the shorted stub can make a resonator. Shielding this kind of resonator by means of vias or stacked vias enables very compact filter designs.

Abstract: Consistent with an example embodiment, there is an integrated circuit (IC) device in a packaging having electrically insulated connections. The IC device comprises a semiconductor device (100) mounted onto a die attachment area (10); the semiconductor device has a plurality of bonding pads (20a, 25a, 30a, 35a). A lead frame having a plurality of bonding fingers (20b, 25b, 30b, 35b) surrounds the die attachment area. A plurality of mutually isolated connection conductors (25d, 30d, 40, 50) having respective first ends are attached to respective bonding pads on the semiconductor device and the plurality of mutually isolated connection conductors having respective second respective second ends are attached to respective bonding fingers of the lead frame. An insulating material (45) coats at least a portion of the plurality of mutually isolated connection conductors.

Abstract: A monotonic variable gain amplifier which can be controlled to achieve a desired gain. The amplifier has: —at least two amplifier stages (41-45) connected in parallel between input and output terminals, each amplifier stage including: * a fixed gain transconductance amplifier (100, 102) through which a bias current (Ibi) flows controlled by the input signal,—a controllable current divider (104, 106) controllable to vary the ratio of the amount of the bias current (Ibi) that is drawn from a first output point to the amount (l1i) of the bias current that is drawn from a voltage source, and—a control loop (190) to keep a DC voltage combined with an outputted amplified DC current at a constant level.

Abstract: The present invention relates to a digital receiver for FM signals, in particular to a new demodulator structure and demodulating method, by which according to a first aspect of the invention the usual complex de-rotation process is reduced to a simple addition/subtraction. According to a second aspect of the invention, the requirements for the sampling frequency necessary for processing the demodulator signals are reduced substantially.

Abstract: Consistent with an example embodiment, there is an apparatus comprising a circuit (500) board. The circuit board includes a first surface (501a) and a second surface (501b). The first and second surfaces each have at least a component populated thereon; the circuit board has a first surface thereof populated before a second surface thereof and is overmolded. The circuit board has conductive material disposed over areas of the second surface defining at least a feature (504) on the second surface. The at least a feature is defined by the conductive material and other than defined by solder resist (508) disposed on the second surface overlapping the conductive material, wherein the at least a feature is a feature for remaining exposed during a process of populating the first surface other than a fiducial.

Abstract: This invention relates to a method of manufacturing a semiconductor device. In this method, a semiconductor device is provided comprising a substrate (10), the substrate (10) being covered with a low-k precursor layer (20) having a surface (25). After this step, a partial curing step is performed in which a dense layer (30) is formed at or near the surface (25) of a low-k precursor layer (20). This dense layer (30) can act as a protective layer (30). The low-k precursor material (20) is chosen from a group of materials having the property that they are applicable in a non-cured or partially cured state. The main advantage of this method is that no separate protective layer (30) needs to be provided to the low-k precursor layer (20), because the dense layer (30) is formed out of the low-k precursor layer (20) itself. The dense layer (30) therefore has a good adhesion to the low-k precursor layer (20).

Abstract: A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.

Abstract: Methods and apparatus suitable for rapid creation and configuration of microcontroller products, which include a microcontroller or similar computational resource, and configurable logic devices are described. Various embodiments of the present invention allow development of new microcontroller-based products and product families in a rapid and cost-effective manner, thereby enabling early entry of such products into the marketplace. An existing microcontroller block and existing configurable logic devices are combined to form a unique product, wherein the microcontroller block is operable to configure the configurable logic devices to form the desired unique hardware characteristics of the microcontroller-based product. The microcontroller block configures the configurable logic devices when the product is reset, and/or when a power-up condition is recognized.

Abstract: The LDMOS transistor (99) of the invention is provided with a stepped shield structure (50) and/or with a first (25) and a second (26) drain extension region having a higher dopant concentration than the second drain extension region, and being covered by the shield.