Abstract: A method of processing a semiconductor substrate (3) comprises spinning the semiconductor substrate (3) while dispensing a reactive etching agent (7) onto a first surface of the spinning substrate (3) to etch a first region (8) of the surface (3). Simultaneously, a neutralising agent (9) is dispensed onto the first surface to neutralise etching agent (9) that has flowed away from the first region (8) of the surface (3), thereby substantially preventing processing of another region (10) of the first surface located nearer an edge of the substrate (3) than is the first region (8). The processing may be etching.

Abstract: There is provided a method of configuring a radio receiver, the radio receiver comprising signal receiving means, and at least one adjustable component coupled to the signal receiving means; the method comprising setting the at least one component to a first value selected from a plurality of values; measuring the quality of a signal received via the signal receiving means and the at least one adjustable component; repeating the steps of setting and measuring for at least a second value selected from the plurality of values; and determining the value of the at least one adjustable component that provides the highest measured signal quality.

Abstract: The invention relates in general to a method for determining cable termination resistances in communication networks and a corresponding communication network, and is applicable especially to high-speed communication networks in automobiles, which uses dual-wire harnesses like FlexRay e.g.

Abstract: A method for coding information in an electronic circuit and an electronic circuit for coding information uses at least two electrically coupled signal paths (X0, X1). Cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first paths (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0). an output signal (X) having a second logic value is produced.

Abstract: A device (1) for processing a signal (S) has firstly an antenna configuration (5) that is arranged to transmit a signal (S), that has at least one antenna-configuration terminal (6, 7) intended for connecting the antenna configuration (5) to a circuit (2), and that has an antenna-configuration impedance (ZA) at the antenna-configuration terminal (6, 7), and the circuit (2) further has at least one circuit terminal (3, 4) at which the circuit (2) has a circuit impedance (ZS) and at which the circuit (2) is connected to the antenna-configuration terminal (6, 7) for the purpose of power transmission between the antenna configuration (5) and the circuit (2) by using the signal (S), at least one of the two impedances (ZA, ZS) having, in respect of its reactance (YA, YS), a difference in reactance value (?Y) from a nominal reactance value (YNOM) that is adapted for the transmission of power between the antenna configuration (5) and the circuit (2), and one of the two impedances (ZA, ZS) having a resistance (XA, XS)

Abstract: A method for adjusting the signal to noise ratio of a receiver comprises measuring the peak power for an RF signal and determining, based on the measured peak power, whether the RF signal power is within a desired operating range. The method further includes adjusting an RF attenuation for the receiver, when it is determined that the RF signal power is not within the desired operating rang. The method further comprises measuring a peak power foe an IF signal, determining based on the measured peak power, whether the IF signal power is within a desired operating range, and adjusting an IF attenuation for the receiver, when it is determined that the IF signal peak power is not within the desired operating range.

Abstract: A driver for a brushless motor (10) is described comprising a static position sensing device (22), a back EMF detector for detecting a back EMF voltage (40), comprising a filter (42). The driver further comprises an output stage (30) with at least three modules (30U, 30V, 30W) for supplying a current to a respective phase coil (11U, 11V, 11W) of the motor (10), and a commutating device (21) for selectively enabling respective modules (30U, 30V, 30W) of the output stage (30) depending on the position ($) of the motor. The selectively enabling is alternated with a commutation frequency (VE). The commutating device (21) is controlled by the static position-sensing device (22) at startup of the motor and by the back EMF detector (40) after the first detected back EMF pulse.

Abstract: The invention relates to an arrangement for driving a display device with columns and rows in which different voltage values may be fed to columns of the display device in dependence upon the data to be displayed. The invention also relates to a display device with a driving arrangement.

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. The element is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract: An electronic device with a CMOS circuit (CC) comprises a first driver circuit (10) having a first and second PMOS transistor (P1, P2) and a first and second NMOS transistor (N1, N2). The electronic device furthermore comprise a second driver circuit (20) with a third and fourth PMOS transistor (P3, P4) and a third and fourth NMOS transistor (N3, N4). The second driver circuit (20) is complementary to the first driver circuit (10) and switches in the opposite direction to the first driver circuit (10). A gate of the second and fourth PMOS transistor (P2, P4) is coupled to a first bias voltage (REPp) and a gate of the second and fourth NMOS transistor (N2, N4) is coupled to a second bias voltage (REFn). A first capacitance (C3) is coupled between the gate and the drain of the fourth PMOS transistor (P4) and a second capacitance (C4) is coupled between the gate and the drain source of the fourth NMOS transistor (N4).

Abstract: Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14).

Abstract: A cell selection device (D) is dedicated to a piece of wireless communication equipment (MS) arranged to establish radio communications with a radio communication network comprising radio communication cells and to receive data representative of the cell environment and of service capabilities of each cell of this environment from the network. This device (D) comprises a control means (CM) arranged, when its equipment (MS) needs to access a chosen network service, to access the data received by the equipment (MS) and representative of the cell environment and the corresponding cell service capabilities, to determine whether there is at least one cell in this environment that allows to access the network service, and to order the equipment (MS) either to pursue or to establish a radio communication with the network via a selected one of these determined cells if the selected cell allows at least one chosen radio parameter criterion to be satisfied.

Abstract: The present invention relates to the implementation for implementing multi-tasking on a digital signal processor. For that purpose blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which in stead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

Abstract: A configuration composed of multiple short emitters still share common DTI regions and a single big piece of base poly. This allows for base current to flow in 4 directions (e.g., 2 dimensions) as opposed to only two. This significantly reduces the base resistance of the transistor that is crucial for better NPN transistor RF performance and high frequency noise performance.

Abstract: A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

Abstract: A system, apparatus and methods are described that select a guard interval length (345) for a multi-path communications channel. In one embodiment, the guard interval length is selected based on a relationship between a selected coherence bandwidth (335) and a RMS delay (340) of the communication channel.

Abstract: According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings on the top-side surface. A laminate material is applied (10) to the top-side surface of the lead frame. In the laminate material, an air-cavity region and contact regions are defined (15, 20, 25, 30, 35). The contact regions provide electrical connections to the predetermined pad landings on the lead frame. With the active circuit surface in an orientation toward the laminate material, the device die is mounted (40, 45). The bond pads of the active surface circuit are connected with ball bonds to the predetermined pad landings on the lead frame. An air-cavity is formed between the active surface of the device die and the top-side surface of the lead frame.

Abstract: A divide-by-n process is effected via a scale-by-four/n process followed by a divide-by-four process. A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By incorporating a terminal divide-by-four process, quadrature output signals are easily provided. A divide-by-three quadrature divider effects the scale-by-4/n process via a selection of every third quadrature clock phase, and the quadrature output of the divide-by-four process provides the control signals to effect this every-third clock phase selection.

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr

Abstract: Display driver (10) with a frame memory (13) for temporarily storing image data representing a color image, and a data bus (11.1) for feeding image data to the display driver (10). The display driver (10) comprises means for performing a decision process (8, 9), said decision process being based on an analysis of the color characteristics of a pixel cluster of said image data, the means for performing a decision process (8, 9) allowing the display driver (10) to decide whether a first compression format or a second compression format is to be applied for compression of said pixel cluster. It further comprises first compression means (7) performing a compression of said pixel cluster into said first compression format, and second compression means (6) performing a compression of said pixel cluster into said second format.