Abstract: A software GPS processing arrangement comprising a FIFO buffer for receiving a stream of the GPS signal samples, a memory, a DMA controller for transferring the GPS signal samples from the FIFO buffer to the memory, a CPU running GPS signal processing software configured to retrieve the GPS signal samples from the memory and process them to obtain a position fix, and a counter operating independently of the DMA controller and the CPU for keeping count of the number of streamed GPS signal samples.

Abstract: A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bitline-bar (BLB). A second pass-gate FET (T1) is coupled between a second node (B) and a bitline (BL). The second node (B) is coupled to the first pass-gate FET (T6) and the first pass-gate FET (T6) is switched according to the voltage (VB) at the second node (B). The first node (A) is coupled to the second pass-gate FET (T1). The second pass-gate FET (T1) is switched according to the voltage (VA) on the first node (A).

Abstract: The present invention, generally speaking, provides interleavers and methods of interleaving that satisfy the need for backward compatibility while effectively addressing competing design objectives. In accordance with one aspect of the invention, data is transmitted using a number of transmit antennas greater than an expected number of receive antennas. At least one pair of transmit antennas is formed, and multiple second data streams are formed from a first data stream, successive bits in said first data stream being assigned to different ones of said second data streams. Block interleaving of multiple respective ones of said second data streams is individually performed. During successive transmission intervals, the pair of transmit antennas is used to transmit a pair of data symbols taken from different ones of said second data streams, followed by an equivalent transformed pair of data symbols.

Abstract: Display driver (10) with a frame memory (13) for temporarily storing image data representing a color image, and a data bus (11.1) for feeding image data to the display driver (10). The display driver (10) comprises means for performing a decision process (8, 9), said decision process being based on an analysis of the color characteristics of a pixel cluster of said image data, the means for performing a decision process (8, 9) allowing the display driver (10) to decide whether a first compression format or a second compression format is to be applied for compression of said pixel cluster. It further comprises first compression means (7) performing a compression of said pixel cluster into said first compression format, and second compression means (6) performing a compression of said pixel cluster into said second format.

Abstract: The present invention relates to adjustment of interconnect power levels in high-speed differential serial links. In an example embodiment, a digital signal received at a digital input port is converted in a driver into a corresponding differential signal and provided to output ports connected to a differential transmission line for provision to a receiver. For adjusting the interconnect power levels between the driver and the receiver a voltage regulator is interposed between a voltage source and the driver. The voltage regulator provides regulated supply voltage to the driver. In operation, the voltage regulator receives from control circuitry a control signal indicative of a predetermined regulated voltage for provision to the driver for a pre-selected type of data transmission. In dependence upon the received control signal the voltage regulator selects the corresponding reference voltage and provides it to the driver.

Abstract: A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.

Abstract: A semiconductor device includes at least one active component (18) having a p-n junction (26) on the semiconductor substrate in an active region (19) of the semiconductor substrate (4). A shallow trench isolation pattern is used to form a plurality of longitudinally extending shallow trenches (12) containing insulator (14). These trenches define a plurality of longitudinal active stripes (10) between the shallow trenches (12). The shallow trench isolation depth (ds?) is greater than the junction depth (dsO of the longitudinal active stripes and the width (wsO of the active stripes (10) is less than the depletion length (ldepi) of the p-n junction.

Abstract: In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern.

Abstract: The invention discloses a method and apparatus for polarization display of antenna. The apparatus for polarization display of antenna comprises a selecting means for selecting a plurality of predetermined radiation directions from radiation directions of an antenna, a mapping means for mapping the plurality of predetermined radiation directions into a coordinates chart, an obtaining means for obtaining corresponding radiation data for the antenna in the plurality of predetermined radiation directions, and a plotting means for plotting a polarization pattern of the antenna in the plurality of predetermined radiation directions on the coordinates chart, according to the radiation data. With the method and apparatus of the invention, all polarization information of the antenna in each radiation direction can be provided with only one FIGURE.

Abstract: A method for circularly accessing a plurality of memory addresses, using a sequence of values comprises determining a plurality of values, the number of values in the plurality of values being m, each value being represented by a predefined number of bits n. The method further comprises identifying in a register (20) of a processor, comprising a plurality of addressable bits ordered by significance, a sequence of m times n consecutive bits, thus having defined a set of m units (21, 22, 23, 24) of n consecutive bits each. It involves initializing each unit of the set of units with the bits representing a different value of the plurality of values, and rotating the identified bits of the register (20) with a number of bits equal to an integer multiple of n. The method also comprises reading a unit for obtaining a value represented by the unit.

Abstract: The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting region (31) and an emitter region (29) are formed simultaneously and self-aligned to the base connecting region (23) without applying photolithographic techniques.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium, further called the silicon-germanium layer (2) and having a lower surface close to the substrate (11) and an upper surface more remote from the substrate (11), and wherein the silicon-germanium layer (2) is subjected to an oxidizing treatment at a surface of the silicon-germanium layer (2) while the other surface of the silicon-germanium layer (2) is protected against the oxidizing treatment by a blocking layer (3).

Abstract: A processor reduces periodic interference signal components in an input signal to obtain a desired signal. The desired signal has a predefined characteristic during an interval of time. First, an interference-representing signal (S1-S13) is stored (SWM1, C1-C13) on the basis of the input signal that occurs within the interval of time during which the desired signal has the predefined characteristic. The interference-representing signal (S1-S13) represents at least one period of a periodic interfering signal. Then, on the basis of the interference-representing signal (S1-S 13), compensation (ICS) is repetitively provided (SWM2, SUB) for the periodic interfering signal.

Abstract: There is a method of manufacturing a semi conductor device that comprises source and drain regions of a first conductivity type, and a channel-accommodating region of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate which extends adjacent to the channel-accommodating region. The method includes the steps of etching a trench into the semiconductor body of the device at a location laterally spaced from that of the gate; and implanting a second conductivity type dopant into the body through the bottom of the trench to form a second conductivity type localised region in the drain region. The dimensions and doping level of the localised level of the localised region in the finished device is such that the localised region and adjacent portions of the drain region provide a voltage-sustaining space-charge zone when depleted.

Abstract: Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a macroblock decode module configured to decode a plurality of context adaptive binary arithmetic coding (CABAC) encoded symbols corresponding to a slice without processor intervention.

Abstract: An integrated circuit (100) has a plurality of inputs (110) and a plurality of outputs (120). In a test mode, a test arrangement including a plurality of logic gates (140) is coupled between the plurality of inputs (110) and the plurality of outputs (120). The logic gates from the plurality of logic gates (140) have a first input coupled to an input of the plurality of inputs (110) and a further input coupled to a fixed logic value source (150). The fixed logic value source (150) is used to define an identification code of the integrated circuit (100), which can be retrieved at the plurality of outputs (120) when an appropriate bit pattern is fed to the plurality of inputs (110).

Abstract: A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so as to be independently operable. The first gate (G31) is a trench-gate (21, 22), and the second gate (G32) has at least an insulated planar gate portion (13, 14). Simultaneous operation of the first (G31) and second (G32) gates forms a conduction channel (23c, 23b) between source (16) and drain (12) regions of the device (3). The device (3) has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device (3) may be a high side power transistor is series with a low side power transistor (6) in a circuit arrangement (50) (FIG. 14) for supplying a regulated output voltage.

Abstract: The cascode circuit comprises a plurality of switching transistors (11) to be protected from high voltage and a plurality of cascode transistors (13) connected to the switching transistors (11). A test node (B?) is arranged between each switching transistors (11) and its cascode transistor (13), and a test transistor (30.1-30.n) is allocated to each test node (B?), its gate being connected to the test node (B?). The sources of the test transistors (30.1-30.n) are connected to a first test point (31) and the drains of the test transistors (30.1-30.n) are connected to a second test point (32). A first voltage (U1) is applied to the first test point (31) and a second, slightly lower voltage (U2) is applied to the second test point (32). A current flow detected between the first (31) and the second (32) test point indicates that at least one of the cascode transistors (13) does not work correctly. Thus, the cascode circuit is testable.

Abstract: A description is given of an arrangement for compensation of ground offset in a data bus system comprising a plurality of communication devices (2, 10) which are each supplied with an operating voltage (U0) by a voltage source (4; 14), are connected to ground (G1); G2) and have a data bus connection (6; 12) via which they are connected to a data bus line (8). The special thing about the invention is that between operating voltage (U0) and ground (G2) at least one voltage dividing device (R3, R6) is connected whose output is coupled to the data bus connection (12) of at least one communication device (10) and whose voltage dividing ratio is selected such that an offset of the ground (G2) of the communication device (10), whose data bus connection (12) is coupled to the voltage dividing device (R3, R6), is in essence compensated compared to ground (G1) of another communication device (2).

Abstract: A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value.