Abstract: A measuring method for measuring physical variables comprises—the selection of a working point (AP) lying within a total measurement range (G) of a physical variable (M) to be measured,—the detection of a measured value (M(t1)) of the physical variable at a first measuring time (t1),—the determination of a displacement value (V(t1)) as the result of a subtraction of the measured value (M(t1)) measured at the first measuring time from the working point (AP),—the formation of change values (C(t2), C(t3) . . . C(tx)) of the physical variable (M) by acquiring subsequent measured values (M(t2), M(t3) . . . M(tx)) of the physical variable at subsequent measuring times (t2, t3 . . . tx) and addition of the displacement value (V(t1)) to the subsequent measured values.

Abstract: The present invention relates to a data-processing device, particularly a chip card or smart card, and to a method of operating said device, with an integrated circuit comprising a central processing unit (CPU) (10) and one or more co-processors (12). The integrated circuit comprises a control unit (18, 30) which controls the processors, CPU (10) and co-processors (12) in such a way that, in the case of a cryptographic operation, at least two processors perform a cryptographic operation simultaneously and in parallel.

Abstract: The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed. DPA is a procedure that makes it possible to obtain not only purely functional details but also internal information stored in integrated circuits (e.g. smart-card controllers). The majority of non-clocked classes of circuit have the property that the performance of the circuit adjusts automatically to the voltage available. The invention adopts a new approach to enable integrated circuits and particularly non-clocked handshake logic to be protected against DPA. Advantage is taken in this case of a special property of self-timed logic by using a special power supply.

Abstract: An integrated circuit 1 comprises a timing closure monitoring circuit 2. The timing closure monitoring circuit 2 comprises a duplicate path 19, having the same characteristics as a logic path 3 being monitored. The duplicate path 19 receives a pulsed reference signal 23 from a reference generating unit (RGU) 24. The pulsed reference signal 23 is synchronized with the clock signal 13, and passed through the duplicate path 19 to a reference checking unit (RCU) 25. In a normal mode of operation in which timing closure is guaranteed, the clock signal 13 will sample the pulsed reference signal 23, such that no interrupt signal is generated on the interrupt line 33. However, in the situation where the reference check unit 25 is clocked by the clock signal 13 prior to the pulsed reference signal 23 being received via the duplicate path 19, an interrupt signal is generated on the interrupt line 33, indicating that timing closure cannot be guaranteed.

Abstract: A method and apparatus are described for asynchronous sample rate conversion, in particular those which use an interpolating filter, especially a polyphase interpolating filter (FB4). The input and output signals have jitter but the polyphase branch signals have no or reduced jitter due to the operation of a jitter removing means such as a phase locked loop. The jitter is reduced only in the polyphase branch signals. Various methods are described for reducing the jitter.

Abstract: In a method of tuning a receiver for a digital signal (MPEG2-TS), an input signal (RF-in) is filtered (In-filt, Band-filt) to obtain a processed signal, a digital figure of merit (BER) is determined (Mix/Osc/IF amp IF-downconv-2, C) from the processed signal, and the filtering step (In-filt, Band-filt) is fine-adjusted (?P, PLL, DAC1-DAC3) in dependence on the digital figure of merit (BER).

Abstract: The invention relates to a method of manufacturing integrated circuits and in particular to the step of forming shallow trench isolation (STI) zones. The method according to the present invention leads to electronic devices and to integrated circuits having reduced narrow width effect and edge leakage. This is achieved by performing an extra implantation step near the edge of the STI zone, after formation of the SU zones.

Abstract: The present invention relates to a metal-interconnect structure for electrically connecting integrated-circuit elements in an integrated-circuit device. It solves several problems of operational reliability in damascene interconnect structures, due to corner effects and structural defects present at top edges of interconnect lines fabricated according to prior-art processing technologies. In alternative configurations of the metal interconnect structure, capping spacers (334) are arranged abutting and covering outer top edges (316c) of interconnect lines (304) or lateral barrier liners (316), respectively. The interconnect structure of the invention eliminates the negative influence of these critical regions in the metal-interconnect structure on the operational reliability of an integrated-circuit device.

Abstract: Methods and wireless communication device for associating UWB (Ultra Wide Band) WPAN devices through the processing of ranging information. Ranging information represents the distance between a device and another device. Devices can automatically determine whether association has occurred via evaluation of, e.g., changes in distance, velocity and/or acceleration of devices, optionally in conjunction with a user-gated technique. The association between two wireless devices is carried out automatically when the distance between them is below a certain threshold. In a different embodiment, said distance information is used together with user-gated information to take a decision on associate or not associate two devices close to each other. Said user-gated information may be a confirmation given by the user to associate, e.g. through a button, etc.

Abstract: Integrated circuit (20) comprising several different voltage rails (V5 to V1) and an on-chip ESD protection circuit. The ESD protection circuit comprises at least one group (21, 22, 23) of ESD clamp devices (C1-C4). The ESD clamp devices (C1-C4) are arranged in a ladder-configuration. This ladder-configuration is characterized in that there is one of the ESD clamp devices interposed between each of the power rails (V5 to V1) and the respective power rail having a next lower voltage. Due to this arrangement an ESD current path is defined between each one of the power rails and the power rail having the next lower voltage. The ESD clamp devices (C1-C4) are off under normal power operation of the integrated circuit (20).

Abstract: A linear transconductor (LT), for instance for a one-cycle controller (OC), comprises i) an operational amplifier (OA) having non-inverting (+) and inverting (?) inputs, a power supply input intended to be connected to a DC voltage (VBAT), and an output (OO), ii) a voltage divider means (R1,R2) comprising a first terminal defining a transconductor non-inverting input (Vin+) and intended to be connected to a first voltage (Vx), and a second terminal connected to the operational amplifier inverting input (?), iii) a resistor (R3) comprising a first terminal defining a transconductor inverting input (Vin?) intended to be connected to a second voltage and a second terminal connected to the operational amplifier non-inverting input (+), v) first (T1) and second (T2) matched transistors having respective sources connected together and to the operational amplifier power supply input, respective common gates connected to the operational amplifier output (OO), and respective drains, the drain of the first transistor (

Abstract: The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal (15) which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.

Abstract: The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a first conductivity type. A first portion of the second layer (2) is transformed into a buried isolation region (15) comprising a first electrically insulating material. A first semiconductor region (6) of the first conductivity type, comprising, for example, a collector region, is formed from a second portion of the second layer (2) adjoining the buried isolation region (15) and a portion of the first layer (1) adjoining the second portion of the second layer (2). Then a base region (7) is formed on the buried isolation region (15) and on the first semiconductor region (6) by transforming the third layer (3) into a second conductivity type, which is opposite to the first conductivity type.

Abstract: An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (10a-d), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit (104) and a current modulator (106) coupled to the integrating circuit (104). Each stage triggers a transition in the next stage when the integration result reaches a level defined by a reference voltage. Correlating circuitry (102, 30, 32, 34) is provided with current outputs to generate currents to the current modulators (106) and reference voltages for the saw tooth delay stages (10a-d). The reference voltages are generated at least partly from a common reference (102c), so that noise in the currents from the current modulators (106) and reference voltages is correlated in a way that at least partly cancels the effect of the noise on the delay time.

Abstract: Display driver (40) with a frame memory (43) for temporarily storing image data representing a color image and a data bus for feeding RGB-formatted image data to said display driver (40). The display driver (2) comprises means for performing an encoding decision process (42) that is based on an analysis of the nature of a pixel cluster of said image data. The means for performing a decision process (42) allow the display driver (43) to decide whether a first compression format or a second compression format is to be applied for compression of said pixel cluster. The first compression means (33.1) perform a compression of said pixel cluster into said first compression format (quantized RGB), and the second compression means (33.2) perform a compression of said pixel cluster into said second compression format (color compressed).

Abstract: A circuit (12) comprises a first circuit point (13) and a second circuit point (14), which first circuit point (13) and second circuit point (14) are designed to be connected with RF transmission means (11) being designed for receiving in a contact-less manner a carrier signal (CS) from a read/write station and for feeding the circuit (12) with the received carrier signal (CS). The circuit (12) further comprises circuit testing means (4) being designed to carry out functional tests of the circuit (12) and to output a modulated response signal (TS-MOD) via the first and second circuit points (13, 14) only if the functional tests have been successful.

Abstract: The invention relates to a method of packaging an electronic microsystem (200) and further to such a packaged device. With the method a packaged electronic microsystem (200) can be manufactured using a flexible foil (80) having conductive tracks (100) on at least on side of the flexible foil. The electronic microsystem (200) and the flexible foil (80) are arranged in a way that a sealed or even hermetic package can be realized and contact pads (210) of the electronic microsystem (200) are connected to conductive tracks (100) extending to the outer surface of the packaged device after folding the flexible foil (80) in the proposed way. No vias or throughholes in the flexible foil (80) are needed.

Abstract: A driver (1) supplies an output voltage (VL) to an inductive load (30). The driver comprises an input to receive a pulse width modulated control signal (CS) having a controllable duty cycle within a predetermined range. A first switch circuit (10) receives a first switch signal (CS; ICS) to supply a first voltage (V1), a second switch circuit (13) receives a second switch signal (DCS; CSD) to supply a second voltage (V2), and the output voltage (VL) is the difference between the first voltage (V1) and the second voltage (V2). An inverter (11; 15) and delay circuit (12; 16) receives the control signal (CS) to supply the first switch signal (CS; ICS) and the second switch signal (DCS; CSD) being inverted and delayed with respect to each other. The delay (dT) of the delay circuit (12; 16) is selected to obtain an output voltage having a single polarity for each one of said controllable duty cycles within the predetermined range.

Abstract: The invention relates to a method and to a semiconductor device, comprising means for detecting an unauthorized access to the semiconductor device, wherein the semiconductor device carries out an initialization of the semiconductor device following detection of an unauthorized access, wherein an information item relating to the unauthorized access can be stored by the semiconductor device prior to the initialization, and wherein the stored information item relating to the unauthorized access remains intact following the initialization of the semiconductor device. It is advantageously provided that the stored information item remains intact for a predetermined period of time following disconnection of the semiconductor device from a power supply.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (1) of silicon is provided, at a surface thereof, with a semiconductor region (4) of a first conductivity type, in which region a second semiconductor region (2A, 3A) of a second conductivity type, opposite to the first conductivity type, is formed forming a pn-junction with the first semiconductor region (4) by the introduction of dopant atoms of the second conductivity type into the semiconductor body (1), and wherein, before the introduction of said dopant atoms, an amorphous region is formed in the semiconductor body (1) by means of an amorphizing implantation of inert atoms, and wherein, after the amorphizing implantation, temporary dopant atoms are implanted in the semiconductor body (1), and wherein, after introduction of the dopant atoms of the second conductivity type, the semiconductor body is annealed by subjecting it to a heat treatment at a temperature in the range of about 500 to about 80