Abstract: The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.

Abstract: An electronic circuit has an output driver (DRV) for providing a driving signal (U0). The output driver has a transistor (T) with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal (Vcntrl), a power supply terminal (VSS), an output terminal (OUT) for providing the driving signal (U0) that is coupled to the second main terminal, and a sensing resistor (Rm) coupled between the power supply terminal (VSS) and the first main terminal. The output driver (DRV) further has means for temporarily disabling the coupling between the control terminal and the control signal (Vcntrl) during a peak voltage across the sensing resistor (Rm). The means may have a circuit that has a unidirectional current behavior, such as a diode (D), in series with the control terminal of the transistor (T).

Abstract: In an example embodiment, there is a method (600) for determining an approximately optimal resist thickness comprising providing a first substrate coated with a resist film having a first thickness using a first coat program, (605, 610). The first thickness of resist is measured (615, 620). A second substrate is provided (625) and coated with a resist film using the first coat program. The resist film on the second substrate is exposed to radiation. The reflectance spectrum near the actinic wavelength of the resist film is measured (630). As a function of the periodicity of the reflectance spectrum, an effective refractive index is determined. Based on the effective refractive index, a periodicity of a swing curve of the resist film coated on the second substrate is determined (635). The maxima and minima are determined as a function of the periodicity.

Abstract: In order to develop an electronic communication system (100; 100?), designed for a progressive movement means, having at least one base station (10) and having at least one carrier station (60) such that the possible uses of this communication system (100; 100?) can also be extended to other important areas of use of a progressive movement means, it is proposed that the carrier station (60) be designed as in each case at least one sensor unit, which is assigned to at least one wheel or tire (90) of the progressive movement means and—which is designed to detect and/or determine at least one characteristic parameter of the wheel or tire (90), such as for example the air pressure and/or the temperature and/or the wear of the wheel or tire (90).

Abstract: The invention relates to the manufacture of a semiconductor device (10) with a semiconductor body (1) and a substrate (2) and comprising at least one semiconductor element (3), which semiconductor device is equipped with at least one connection region (4) and a superjacent strip-shaped connection conductor (5) which is connected to the connection region, which connection region and connection conductor are both recessed in a dielectric, and a dielectric region (6) of a first material is provided on the semiconductor body (1) at the location of the connection region (4) to be formed, after which the dielectric region (6) is coated with a dielectric layer (7) of a second material that differs from the first material, which dielectric layer is provided, at the location of the strip-shaped connection conductor (5) to be formed, with a strip-shaped recess (7A) which overlaps the dielectric region (6) and extends up to said dielectric region, and after the formation of the recess (7A) and the removal of the dielect

Abstract: A circuit arrangement for obtaining an output signal (Va) form a signal (Vs) containing at least one alternating component comprises a signal source (1) that supplies this signal (Vs), a first peak value detection device (2) for determining a maximum value (Vmax) of the signal (Vs), a second peak value detection device (3) for determining a minimum value (Vmin) of the signal (Vs), a first signal linking device (4, 5, 6, 71) for obtaining a first resulting signal (V1) by additive linking of the signal (Vs), the maximum value (Vmax) and the minimum value (Vmin) in accordance with the rule: V1=K1*{Vs?(Vmax+Vmin)/2}, in which K1 is a freely selectable first constant factor, a second signal linking device (7, 72) for obtaining a second resulting signal (V2) by additive linking of the maximum value (Vmax) and a minimum value (Vmin) in accordance with the rule: V2=(Vmax?Vmin)*K2, in which K2 is a freely selectable second factor, a first squaring device (8) for squaring the first resulting signal (V1), a second squar

Abstract: A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.

Abstract: A method of negotiating a proper communication protocol between a reader device (10) and a data carrier (20) is disclosed. In a first step, when the data carrier (20) is inserted into the reader device (10) at a first point in time (t1), the data carrier (20) provides information to the reader device (10), which communication protocols are supported by the data carrier (20), by means of a binary value (BV). In a next step, the reader device (10) chooses/sets one of the possible communication protocols according to its own capability. This choice is provided to the data carrier (20) by applying a clock signal (CLK) of a certain frequency (f), which is associated with the chosen/set communication protocol, to an input contact (C3) of the data carrier (20) at a second point in time (t2). Finally, the data carrier (20) sets the chosen communication protocol received from the reader device (10), thereby finalizing the negotiation sequence.

Abstract: The present invention, generally speaking, provides interleavers and methods of interleaving that satisfy the need for backward compatibility while effectively addressing competing design objectives. In accordance with one aspect of the invention, data is transmitted using a number of transmit antennas greater than an expected number of receive antennas. At least one pair of transmit antennas (ant?_1, ant?_) is formed, and multiple second data streams (610a, 610u) are formed from a first data stream, successive bits in said first data stream being assigned to different ones of said second data streams. Block interleaving of multiple respective ones of said second data streams is individually performed (611a, 611u). During successive transmission intervals (617), the pair of transmit antennas is used to transmit a pair of data symbols taken from different ones of said second data streams, followed by an equivalent transformed pair of data symbols.

Abstract: A circuit arrangement and method utilize a variable threshold, multi-stage pulse shaping circuit to pulse shape a signal output by a crystal oscillator circuit. Each stage of the pulse shaping circuit includes a Schmitt trigger that drives an input of a latch, and that has a programmable trip point controlled to reject distorted pulses generated by the crystal oscillator circuit. A variable threshold, multi-stage pulse shaping circuit may be used, for example, to generate a clock signal for an electronic circuit that is more resistant to noise and other environmental effects, thereby reducing the likelihood of clock-related errors in the electronic circuit.

Abstract: A method of powering up a portable terminal, which automatically executes a software program when powered on, the terminal having a manually operated power-up key, wherein the method comprises the step of: a) at the beginning, moving (in 32) the key from an idle position in which the terminal is powered off to an active position in which the terminal is powered up, then b) before a first predetermined time interval (?1) has elapsed since the beginning of step a), starting (in 36) to run the software program on the terminal, the first time interval being long enough to check that the key has not been inadvertently moved, then c) when the first time interval elapsed, if the key is still in the active position, continuing (in 42) to run the software program, else powering down the terminal (in 40).

Abstract: There is provided a method that comprises identifying a parasitic signal transfer in a filter using a signal-directed graph; and adding compensation paths to the filter to reduce or eliminate the effect of the parasitic signal transfer A corresponding filter is provided which comprises a plurality of amplifier stages that generate one or more filter poles; at least one component coupled to at least one of the amplifier stages, the component causing a parasitic effect in the filter; and means for applying a compensation current to the at least one amplifier stage to reduce or eliminate the parasitic effect.

Abstract: A filter weight estimation device (D), for an equaliser of a communication receiver, comprises i) a tap delay line connected to N branches each comprising a descrambler (DS1-DSN) and a despreader (DE1-DEN), for despreading received signals, corresponding to one or more available multiplexed channels associated with different channelization codes, with a reference code equal to the sum of all the channelization codes associated to the available multiplexed channels, Ë) an adaptive filter (AF) comprising N input filter taps respectively connected to the N branches and a regression input and arranged to estimate the sum of the symbols outputted by the despreaders (DE1-DEN) and associated to each available channel, said symbol sum constituting a pseudo-symbol estimate defining a reference symbol estimate (rs), and to implement a mechanism of a LMS type to deliver a chosen number of filter weights (fi), iË) a quantiser (SM) arranged to quantise the reference symbol estimate (rs) to estimate a desired reference sym

Abstract: A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made.

Abstract: A method of making a trench MOSFET includes forming a layer of porous silicon (26) at the bottom of a trench and then oxidizing the layer of porous silicon (26) to form a plug (30) at the bottom of the trench. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.

Abstract: The circuit for controlling the oscillation frequency of an oscillation loop (66) has among others the following components—a first tunable capacitor unit (80) for providing a selectable amount of capacitance to the oscillator loop in accordance with a stored setting, and for controlling the oscillation frequency of the oscillator loop, and—a volatile storage unit (84) adaptated to store the setting of the tunable capacitor unit. The circuit further comprises a supply line (52) to the volatile storage unit and at least one other supply line (44) for the other components of said circuit. The supply line to the volatile storage unit is independent of said at least one other supply line, so that the volatile storage unit can be powered independently of other components of said circuit.

Abstract: A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux(122) by a package (106) including a magnet (120). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.

Abstract: A field effect device includes at least one segmented field plate, each of the at least one segmented field plates having a plurality of segments that each form a plate of a capacitor, wherein the field effect device is connected to an electronic element that dynamically connects selected segments to selectively set a gate-to-drain and a drain-to-source capacitance. An ultrasonic device includes a transducer coupled to a switching device that switches the transducer between a transmit mode and a receive mode switching device, wherein the switching device includes the field effect device.

Abstract: Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a type of access and designating one or several memory locations (46a-d, 47a-b) arranged in accordance with a sequence suitable for said request, processing the requests in accordance with a successive sequence so as to transfer, for each processed request, data from the designated memory location to the data processing circuit, or vice versa, the processing of a request (46) designating memory locations (46a, 46b, 46c, 46d) associated with several banks (A, B, A, B) authorizing a transfer of data between the interface and the memory locations in a sequence which is different from the sequence associated with said request.

Abstract: An automatically configurable smart card comprises—a generic data structure provided for containing smart card specific data, and—a smart card operating system being adapted to automatically detect the generic data structure and to migrate the generic data structure.