Abstract: An oscillator circuit is described comprising a piezoresistive resonator and a phase changing devices. Oscillator circuits with piezoresistive resonators do have the advantage that they can perform self-sustaining oscillation without additional active devices as e.g. transistors since they can be used as amplifiers. Phase changing devices as capacitors, coils and further piezoresistive resonator are used in order to compensate the ?/2 phase shift of the piezoresistive resonator.

Abstract: In order to further develop a circuit arrangement for as well as a method of performing an inversion operation in a cryptographic calculation, wherein only inversion modulo an odd number is allowed, it is proposed that the inversion operation is performed modulo at least one even number.

Abstract: The present invention relates to a improved feedback circuit for generating a quantized control signal representing the relation of a signal to be controlled relative to predetermined limits of at least one error signal window, the circuit comprising signal detecting means, a detected signal connected to error amplifying means for amplifying the error between the detected signal and a first reference signal, the output error signal of the error amplifying means connected to at least a first comparator means and second comparator means each configured to compare the error signal with one of the upper limit and lower limit of the at least one error signal window. The invention provides a circuit and method by which only one accurate comparator is needed and for the error windows only simple, inaccurate comparators can be used.

Abstract: A receiver comprises two tuners and a DC-to-DC converter (DCC) for generating an increased supply voltage (VH) on the basis of a main supply voltage. Each tuner comprises a tunable circuit (TUC1), which can be tuned by means of a tuning voltage (VT1). Each tuner further comprises a tuning control circuit (TCC1) that is coupled to the DC-to-DC converter (DCC) via a load circuit (LD1) for generating the tuning voltage (VT1). The load circuit (LD1) of at least one of the two tuners comprises a branch (D1) coupled to receive the main supply voltage (VCC). The branch (D1) is conductive when the tuning voltage (VT1) is within a voltage range substantially comprised between 0 and the main supply voltage (VCC).

Abstract: A symbol-level adaptation method to adapt at least one coefficient of an equalizer, wherein the method comprises the steps of: a) executing an adaptive algorithm that calculates the value of the equalizer coefficient, the adaptive algorithm having a tunable parameter that determines how the calculated coefficient value is close to the optimal solution b) modifying the value of the equalizer coefficient according to the calculated coefficient value at an intermediate instant t? strictly between two consecutive instants tA and tB, instants tA and tB corresponding to the beginning and the end of a pilot symbol period respectively, and c) adjusting the value of the tunable parameter according to a number ? representing the number of chips yet to be received before instant tB or already received since instant tA.

Abstract: A multi-mode WLAN-GSM communications device (100) comprises a WLAN transmitter (110) that stalls its transmit data and depowers its radio transmitter whenever a collocated GSM receiver (104) signals it needs to receive a GSM base-station transmission. If a collocated Bluetooth device is also included, the Bluetooth receiver can also signal the WLAN transmitter (110) to be quiet during selected timeslots.

Abstract: An electronic circuit has a signal conductor (11), a power supply reference conductor (10) connected by a switching circuit. The switching circuit contains a PMOS transistor (17) and an NMOS transistor realized on a common substrate (100). The NMOS transistor (17) has a source coupled to the power supply reference conductor (10). The NMOS transistor (18) has a source coupled to the drain of the PMOS transistor (17), and a drain coupled to the signal conductor (11). A control circuit (13, 14, 15, 16) switches between an “on” state and an “off” state, in which the control circuit (13, 14, 15, 16) controls the gate source voltages of the first and second MOS transistor (17, 18) to make channels of these MOS transistors (17, 18) conductive and not to make the channels of these first and second transistors (17, 18) conductive respectively. Preferably a complementary switching circuit is also provided.

Abstract: A method and circuit for preserving linearity of a RF power amplifier, the power amplifier including a RF power output unit (4, 24, 62) having a characteristic drive level and fed by a supply voltage, comprising measuring the output voltage of the RF power output unit (4, 24, 62); comparing the measured output voltage to at least one threshold voltage to produce a control signal; and adapting the drive level or the supply voltage of the RF power output (4, 24, 62) unit by means of the control signal to operate the output unit below its saturation level. A method and circuit for stabilizing an antenna circuit comprising a RF power amplifier and a matching circuit by preserving linearity of a RF power amplifier, where the above power amplifier is used.

Abstract: An integrated circuit comprising a plurality of modules (M) for processing applications is provided, wherein each of said modules comprise a local memory (LM). The integrated circuit further comprises a global memory (GM), which can be shared between the plurality of modules (M), and an interconnect means (IM) for interconnecting said modules (M) and said global memory (GM). A memory managing unit (MMU) is associated to each of said modules (M) and determines whether the local memory (LM) provides sufficient memory space for the currently processed application. If this is not the case, the memory managing unit (MMU) requests a global buffer (FB) in said global memory (GM) to be exclusively reserved for the processing data of its associated module (M). Accordingly, by using the local memory (LM), whenever possible, before data is outsourced to the global memory (GM), power as well as bandwidth of the interconnect means can be saved.

Abstract: The present invention relates to a non-volatile memory device, comprising a memory array (10, 20) with a plurality of memory cells (100, 200) arranged in rows and columns, bit line conductors (12, 22) coupled to said rows of memory cells, an averaging circuit (11, 21) with inputs coupled to a plurality of said bit line conductors (12, 22) and being arranged to determine an average level on respective analog signal levels on said plurality of bit line conductors (12, 22), a monitoring circuit (13, 23) coupled to said averaging circuit (11, 21) and being arranged to monitor said average level and to output a refresh command when said average level shows a predetermined behavior, and a refresh circuit (15, 25) coupled to said monitoring circuit (13, 23) and being arranged to refresh at least a selection of said plurality of memory cells (100, 200) in response to said refresh command.

Abstract: A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.

Abstract: A planar antenna assembly comprises a Planar Inverted F Antenna mounted on a printed circuit board (PP) and comprising i) a radiating element (RE1, RE2) comprising first (RE1) and second (RE2) parts approximately perpendicular one to the other and being respectively located in a first plan facing and parallel to a ground plane mounted on a face of the printed circuit board (PP) and in a second plane perpendicular to said ground plane, ii) a feed tab (FT) extending from said second part (RE2) to said printed circuit board (PP), and iii) a main slot (SO1) having a chosen length and comprising a linear part (LP) defined in the second part (RE2) at a chosen location between lateral sides of the radiating element (RE1, RE2) and a meandered part (MP) extending the linear part (LP) into the first part (RE1).

Abstract: An integrated circuit (1) that comprises an internal clock circuit (12) with a clock output for clocking functional circuits (10) of the integrated circuit (1). The integrated circuit is provided with a counter circuit (16) and a state holding circuit (18) for use during testing. The integrated circuit is switched to a test mode and a start of a test time interval is signalled. Clock pulses from the internal clock circuit 12 are counted from the start of the test time interval and the state holding circuit (18) is locked into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval. Information about whether the state holding circuit (18) has reached the predetermined state in the test time interval is read from the integrated circuit (1) and the information is used by a test evaluation apparatus (2) to accept or reject the integrated circuit (1).

Abstract: The present invention provides for a digital receiver arrangement and related method, in which a digital receiver arrangement comprises a tuner/demodulator circuit, an analogue-to-digital converting means, and further includes means for storing an impulse wavelet representation, means for determining if an interference impulse is present in a received signal, and means for introducing the stored representation of the impulse wavelet to a detected received impulse so as to counteract the effect thereof within the received signal.

Abstract: The invention relates to a so-termed punchthrough diode (10) with a stack of, for example, n++, n?, p+, n++ regions (1,2,3,4). In the known diode, these semiconductor regions (1,2,3,4) are positioned in said order on a substrate (11). The diode is provided with connection conductors (5,6). Such a diode does not have a steep I-V characteristic and is therefore less suitable as a TVSD (=Transient Voltage Suppression Device). In particular at voltages below 5 volts, a punchthrough diode could form an attractive alternative as TVSD. In a punchthrough diode (10) according to the invention, a part of the first semiconductor region (1) bordering on the second semiconductor region (2) comprises a number of sub-regions (1A) which are separated from each other by a further semiconductor region (7) of the second, for example p+, conductivity type which is electrically connected to the first connection conductor (5).

Abstract: A transmitter comprises a power amplifier which has an amplifier power-supply input and an output to supply a transmission signal with an output power. A power supply has power supply outputs to supply a first power supply voltage and a second power supply voltage. A switching circuit is arranged between the power supply outputs and the amplifier power-supply input. A controller has an input to receive a power change command to control: first the switching circuit to supply the first power supply voltage to the amplifier power-supply input, and the power supply to vary a level of the second power supply voltage, the level of the second power supply voltage being lower or higher than a level of the first power supply voltage if the power change command indicates that the output power has to decrease or increase, respectively, and secondly the switching circuit to supply the second power supply voltage to the amplifier power-supply input.

Abstract: Groups of streams of encoded data having different predetermined bit rates are selected for transmission to a client application based on available bandwidth. Common values for at least a part of the decoding parameters are determined so that the decoder can use the same decoding parameter values for decoding stream elements within each group of streams of various bit rates.

Abstract: Stations like mobile terminals, bases stations and network nodes comprising rake receivers with fingers require relatively many calculations to be performed for despreading a symbol. By replacing despreading multipliers, integrators and dumpers in the fingers by Hadamard transformers (62), chips of several symbols with orthogonal channelization codes can be despreaded simultaneously, and the station and the rake receiver have become more efficient. The despreading section (60 of the finger (34) comprises the Hadamard transformer (62) and a serial-to-parallel converter (61) comprising downsamplers (71-73). The station is a high-speed downlink packet access station (HSDPA) in a universal mobile telecommunication system (UMTS), with a number of de-channelization codes used being at least ten percent of a despreading factor used.

Abstract: To provide a method of operating a shielded connection where signals are exchanged between two nodes (1) on a communications network over a connecting line (5a, 5b) and the connecting line (5a, 5b) has a shield (3), by which method can be established that the shield (3) is in a proper state, it is proposed that when a signal is transmitted from a first node (1) over the connecting line (5) to a neighboring node a current (Ishield) is drawn into the shield (3) and when operation is taking place in other ways the shield (3) is set to a bias voltage (UBias). A suitably arranged communications network is also specified.

Abstract: A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages (10c,d) are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned (10c,d) requires writing. A write sequencing circuit (144) performs write tests alternately for instruction dependent information in the first and second one of the stages (10c,d). When the write sequencing circuit (144) performs the write test for a particular one of the stages (10c,d), it tests whether the instruction dependent information in the particular one of the stages (10c,d) requires writing of a result.