Abstract: To further develop a circuit arrangement (100; 100?), and in particular an application circuit, that is arranged to generate at least one test pattern, and a method of testing and/or diagnosing the circuit arrangement (100; 100?) in such a way that reliable fault detection is ensured, it is proposed that the test pattern be remodelable and/or extendable into at least one presettable and/or deterministic test vector by means of at least one test pattern remodeling/extending element (10, 12, 14; 10?, 12?, 14?, and in that—the at least one test pattern remodeling/extending element (10, 12, 14; 10?, 12?, 14?) is arranged, and in particular is inserted, upstream of at least one, and in particular upstream of each, branch point (52, 54, 56) on the at least one signal path (50).

Abstract: A transistor comprises a nanowire (22, 22?) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).

Abstract: A thermal interface material (130) facilitates heat transfer between an integrated circuit device (120) and a thermally conductive device (140). According to an example embodiment, a thermal interface material (130) includes carbon nanotube material that enhances the thermal conductivity thereof. The interface material (130) flows between an integrated circuit device (120) and a thermally conductive device (140). The carbon nanotube material conducts heat from the integrated circuit device (120) to the thermally conductive device (140).

Abstract: A serial data communication system (10) comprises—a local clock generation device (12) adapted for generating a clock signal (16) with a duty cycle depending on a control signal (18), and—a serial data communication control device (14) adapted for generating the control signal (18) depending on the receipt of a serial data signal and for deriving a transmit and receive clock signal (20, 21) from the clock signal (16) received from the local clock generation device (12).

Abstract: The invention relates to a read only magnetic information carrier (1b, 1c, 1d) comprising a substrate (2), an information layer (3) and a stabilizing layer (15a, 15b). The information layer (3) comprises a pattern of magnetic bits (4) of magnetic material wherein the pattern of magnetic bits (4) constitutes an array of bit locations. The presence or absence of the magnetic material at a bit location represents a value of the bit location by a magnetic field (5) having a predetermined magnetization direction (6). The stabilizing layer (15a, 15b) is arranged between the substrate (2) and the information layer (3) and comprises hard magnetic material (8, 9) which is magnetically coupled to the magnetic material of the magnetic bit (4). The magnetically coupled hard magnetic material (8, 9) provides the predetermined magnetization direction (6) of the magnetic field (5).

Abstract: The radio telecommunication terminal (2) comprises a data burst scheduler able to schedule the continuous transmission of consecutive data bursts which generate noise of similar energy on the radio-frequency channel as long as a specific radio-frequency channel is used to receive a radio signal, the respective energy of the noise generated by the transmission of two consecutive first and second data burst being similar only if the noise energy gradient between the end of the transmission of the first data burst and the beginning of the transmission of the second data burst is situated between predetermined upper and lower limits.

Abstract: A video-processing device is provided for processing a main video data flow and a secondary video data flow. The secondary video data flow constitutes a scaled version of the main video data flow. The video-processing device comprises a tap-off unit (T, T2) having an input for receiving the main video data flow. The tap-off unit (T, T2) comprises at least a first and second output, wherein each of the outputs corresponds to the input of the tap-off unit. A first H- and V-scaling unit (HVS1) is coupled to the first output of the tap-off unit (T, T2) for performing a first H- and V-scaling on the main video flow. A second H- and V-scaling unit (HVS2) is coupled to the second output of the tap-off unit for performing a second H- and V-scaling on the secondary video flow to provide a scaled secondary video flow. By tapping-off the main video flow there is no need for the device to access a memory to extract the video data from the main video flow to provide a secondary video flow.

Abstract: A tamper-proof reference usable as a time reference and an integrated circuit apparatus using the tamper-proof reference to determine an elapsed time are disclosed. The circuit comprises a reference source (200) contained in an integrated package comprising a radioactive material (210), a measurement circuit (220) in contact with the radioactive material (210), the measurement circuit for collecting for a predetermined period radiation generated by the radioactive material (210) and a processor (110) in communication with the reference (200), the processor (110) for initiating a measurement by the reference (200) and for determining an elapsed time based on a plurality of measurements by the reference (200).

Abstract: It is described a circuit and a method for transforming an input signal into a logical output. The circuit (100) comprises an inverter stage (120), connected in between the first conductor (101) and the second conductor (102). The inverter stage (120) includes a MOS switch (MP0), which comprises a first terminal being connected to the first conductor (101), a second terminal being connected to an output node (hyst), a gate terminal being connected to an input node (JN), and a back gate terminal. The circuit (100) further comprises a voltage divider (130), connected in between the first conductor (101) and the output node (hyst), wherein the voltage divider (130) provides a divider output node (bg) being connected to the back gate terminal. The circuit (100) represents an input cell having an improved hysteresis behavior over the total operating voltage range. This is achieved by adjusting the back gate voltage of the MOS switch (MP0) during a transition from an input level Low to an input level High.

Abstract: A dual-channel network with in each case one communication controller (2, 6) for each of the two channels (A, B). In order to ensure that the two channels (A, B) operate on a temporally matched basis, an exchange of current states (“ready, “abort”) takes place via an external or an on-chip interface (1a, 1b). The cold start operation is carried out only if, and so long as, both communication controllers are in the “ready” state.

Abstract: Consistent with example embodiments, there is a system and method for providing a built-in characterization of a semiconductor device. The device is provided with a built-in, integral, characterization unit allowing characterization of the device without the need for external test equipment.

Abstract: Magnetic shielding is provided using a variety of methods, systems, devices and circuits. Aspects of present invention provide a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials. The circuit is actively shielded from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device can provide shielding for strong disturbing magnetic fields.

Abstract: A word line driver circuit (10) is coupled to word lines (18) of a memory matrix, for example a matrix of content addressable cells (12). The word line driver circuit is capable of selecting a plurality of word lines simultaneously to permit writing into memory cells in a plurality of rows via the same bit line simultaneously. Cell strength control circuitry (17) reduces a drive strength required to write data into the cells, relative to a drive strength of the bit line driver circuits (15), at least during writing data into memory cells in a plurality of rows of memory cells. Preferably, the drive strength control circuitry (17) contain a resistive element in the power supply lines of the memory cells in a column, so that the supply voltage of the cells in the column is increasingly reduced when more current is drawn during writing of more cells simultaneously.

Abstract: A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.

Abstract: A ladder filter comprising a plurality of bulk acoustic wave resonators, the resonators comprising a plurality of series resonators series resonators in series between an input terminal and an output terminal of the filter, and one or more shunt resonators each connected between a junction between two series resonators and a common terminal, the series resonators comprising an input series resonator connected to the input terminal and an output series resonator connected to the output terminal, and wherein the shunt resonators are designed to satisfy: a unity aspect ratio and wherein the series resonators are designed to satisfy an aspect ratio different from unity. The aspect ratio is defined as the ratio of length to width of the resonator.

Abstract: In order to further develop an electronic memory component (100 or 100?), comprising at least one memory cell matrix (10) which is embedded in and/or let into at least one doped receiving substrate (20), in such a way that a light incidence taking the form of a so-called light attack is detected directly or sensed immediately without dead times (=contribution to chip development), it is proposed,—that the receiving substrate (20) be covered and/or surrounded at least partially and/or on at least one of its surfaces remote from the memory cell matrix (10) by at least one top/protective substrate (30) oppositely doped to the receiving substrate (20) and—that at least one of the substrates (20 or 30), for example the receiving substrate (20) and/or in particular the top/protective substrate (30), be in contact (12a or 12b) or connection (32) with at least one circuit arrangement (24 or 34 respectively) for the detection of voltages or currents caused by charge carriers generated upon light incidence.

Abstract: A radio-frequency ??-modulator comprises a first mixer in the forward path for down-converting the signals in this forward path with a local oscillator frequency and a second mixer in the feedback path for up-converting the feedback signal with the same local oscillator frequency. Delays between the two mixing operations cause a loss of gain in the loop of the ??-modulator. An adjustable amplifier in the feedback path compensates for this loss of gain.

Abstract: The present invention relates to a communication device (28) adapted to communicate with at least one second communication device (26) in a half-duplex near-field communication scheme, and to a method of near-field communication. According to the invention the first communication device (28) receives a first request message (30) from the second communication device (26) which is supposed to be answered within a first response waiting time span (bRWT), and which contains an amount of request data. The first communication device (28) sends within the first response waiting time span (bRWT) a second request message (34) to the second communication device (26), the second request message (34) representing a request for a second response waiting time span (RWT(m)) for providing a first response message (32) in reply to the first request message (30).

Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).