Abstract: It is described an Electro Static Discharge protection, wherein diodes are arranged on two electric paths both extending in between two conductors which are connected with input terminals of an ESD sensitive electronic component. Each path comprises two diodes arranged in series and with opposite polarity with respect to each other. At least one of the totally four diodes comprises a different reverse breakdown voltage. The protection circuit is formed integrally with the ESD sensitive electronic component. Due to the serial connection of two diodes in each path the corresponding ESD protection circuit comprises an extremely low capacitance.

Abstract: In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.

Abstract: A system and method for Cartesian modulation achieved via generation of a three-level pulse width modulated signal. The system in overview comprises two binary pulse width modulated signal generators receiving signals related to the in-phase and quadrature components of a base-band signal and a combination and amplification stage that combines the signals provided by the two binary pulse width modulated signal generators. The binary pulse width modulated signal generators contain at least one signal comparator and at least one base-band pre-distortion element. The signals related to the in-phase and quadrature components of the base-band signal may be; the positive or negative parts of the in-phase component, the positive or negative parts of the quadrature component, the absolute value or sign of the in-phase component, or the absolute value or sign of the quadrature component. These signals may be distorted by a base-band pre-distortion element before being coupled to the comparators.

Abstract: A diversity FM radio receiver comprises two tuners for simultaneously tuning to the same FM channel. To avoid disturbances between the local oscillator signals of the tuners and to be able to use standard IF filters, one of the tuners operate with high-side LO injection and the other tuner operates with low-side LO-injection. To equalize the frequencies of the signals to be subjected to the diversity operation the two IF-signals of the tuners are fed to complex mixers with oppositely rotating phases.

Abstract: A power delivery system for a microprocessor or other ASIC. The power delivery system includes a plurality of cascaded buck stages connected in series, wherein a last buck stage in the plurality of cascaded buck stages provides an output voltage Vo in response to an input voltage Vin applied to a first buck stage of the plurality of cascaded stages. A duty cycle control regulates a duty cycle of each buck stage to maintain the output voltage Vo. The duty cycle control sets the duty cycle of the first buck stage of the plurality of cascaded buck stages to 1 if an input-to-output voltage ratio (Vin/Vo) is lower than a threshold input-to-output voltage ratio RT.

Abstract: In the case of a method of detecting a signal edge in a signal with temporally successive signal edges, there are performed, after triggering by an interrupt signal (IS) generated in an analog/digital converter (13), detection of a rise-representing rise value between two detected amplitude values with subsequent assessment of the rise value together with detection of signal edge direction information and signal edge occurrence information. Further use of this signal edge information is dependent on an additionally detected and assessed signal strength value, which signal strength value is formed from a sum of further amplitude values.

Abstract: An apparatus processes a video stream signal. The video stream signal represents a succession of frames, comprising a plurality of dependent frames that each provide for prediction of visual content using selectable ones of a preceding and following anchor frame that precede and follow the plurality of frames respectively. When a shortage of transmission bandwidth occurs, the apparatus generates a processed version of the video stream signal wherein a bit-rate alteration is performed starting from one of the dependent frames before an end of said plurality. Said alteration is executed by substituting a standard prediction from the following anchor frame at least for data in the video stream signal that encodes a region in said one of the dependent frames.

Abstract: A receiver (13) of user equipment, UE, (10) of a Universal Mobile Telecommunications System, UMTS, network receives a digitally encoded radio signal over a downlink (11) from a base station (12). A Digital Signal Processor, DSP, (14) of the UE (10) estimates BER of data bits of power control commands received in the signal during an out of synchronisation procedure. More specifically, the DSP (14) samples the amplitude with which the data bits are received and determines a ratio of functions of one or more moments of the sampled amplitudes. The DSP (14) then compares the determined ratio to one or more values of BER for different ratios in a look-up table to estimate BER.

Abstract: The present invention discloses a compilation method of a program code in a digital device in a profile driven compilation. An approach for optimizing the execution of program code by providing additional intelligence to the compiler is provided, where the compiler decides whether to have single decision tree with guarded operations or multiple decision trees. The method of this invention is helpful, in reducing the overhead of conditional code branching to have an optimised program code, both in compiler driven optimisations and in manual optimisations by the programmer.

Abstract: A data processing arrangement (MPS) comprises a plurality of data processors (SPR, PM1, . . . , PM4) that can be reset individually. A reset module (RSM) handles various reset request signals (HRG, SRG, SRP1, . . . , SRP4) in accordance with a prioritization and timing scheme so as to obtain respective reset signals (GRS, PRS1, . . . , PRS4) for respective data processors (SPR, PM1, . . . , PM4). The reset module (RSM) preferably comprises a reset request register, which stores respective reset requests that the respective reset request signals convey, and a request execute register, which stores respective granted reset requests that the reset signals convey.

Abstract: A method and system for secure RFID system communication is provided. The RFID system comprises an RFID reader (101) communicating with an RFID tag (102). The RFID reader (101) sends (116) to the RFID tag (102) a request to write. The RFID tag (102) generates random data (P), and sends (122) the random data (P) to the RFID reader (101). The RFID system encrypts information (M2) by using the random data (P), and the RFID reader (101) sends (124) the encrypted information (E) to the RFID tag (102) which decrypts the information (E) by using the random data (P). Finally the RFID tag (102) stores (126) the decrypted information (M2) on a memory (103) of the RFID tag (102).

Abstract: The invention provides a method and apparatus used in a receiver for sampling RF signals, particularly to provide a method and apparatus for greatly decrease the sampling rate performed in RF band. The invention provides an apparatus for sampling a RF signal including a plurality of interference frequency components and a useful frequency component, comprising: a filtering unit for filtering out at least one preset interference frequency component from the RF signal to generate a notch-filtered RF signal; a sampling unit for sampling the notch-filtered RF signal at a preset sampling rate to generate a discrete analog signal. The sampling unit can be implemented by a plurality of notch filters. RF sampling can be simply and conveniently implemented by using the method and apparatus according the invention, and the sampling rate can be decreased to about 1/N of the carrier frequency of the useful frequency component, which is much lower than the sampling rate in existing RF sampling scheme.

Abstract: A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module, wherein the at least one module incorporates at least one associated module monitor suitable for monitoring a device parameter such as temperature, supply noise, cross-talk etc. within the module.

Abstract: The invention relates to a method for increasing the sensitivity of a chain of amplifiers that comprises the steps of amplifying a signal by means of a first amplifier with a gain factor A1=A1,m*?A1, where A1,m denotes a constant gain factor and A1 denotes a gain factor variation with 1?A1,min?A1?A1,max, further amplifying the signal by means of a second amplifier with a controllable gain factor A2?A2,max, where variations A1 of the gain of the first amplifier are compensated by reducing the gain A2 of the second amplifier, so that the difference between the chain gain factor AC=A1*A2 and a target chain gain factor AT?AT,max becomes zero.

Abstract: A power amplifier (100) suitable for use in mobile telecommunications equipment has a first stage (2) and an optional second stage (2), each stage being provided with a bias circuit (4, 5). To provide a well-defined gain characteristic, in the first stage (1) a bias current (Ib1) is fed into a signal amplifying transistor (T1). The first bias circuit (4) comprises non-linear a voltage/current converter (41) coupled to a current mirror (40). To suit alternative applications, such as GSM and UMTS requiring a different bias, plural voltage/current converters (41, 42) may be provided in parallel.

Abstract: A power insulated gate field effect transistor has main cells (2) controlled by a main cell insulated gate and sense cells (4) controlled by a sense cell insulated gate. A sample and hold circuit (10,50) is arranged to operate in a plurality of states including at least one sample state and a hold state to sense the current flowing through the sense cells (4) when in the at least one sample state but not in the hold state. The sample states may be used in a feedback loop to control a drive amplifier (20) driving the gates of the main and sense cells (2,4) and/or to mirror the current in the sense cells (4) on a measurement output terminal (58).

Abstract: According to an example embodiment, there is a testing device for testing a phase locked loop having a power supply input. The testing device comprises a power supply unit for providing a power supply signal VDD having a variation profile to the power supply input of the phase locked loop, wherein a width and height of said variation profile are formed in such a way, that the voltage controlled oscillator is prevented from outputting an oscillating output signal. There is a means for disabling a feedback signal to a phase comparator of the phase locked loop such that said phase locked loop is operated in an open loop mode, and a meter for measuring a measurement signal of the phase locked loop, while said power supply signal is provided to the power supply input.

Abstract: The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.

Abstract: A method (100) is disclosed for communicating data over a data communication bus (310) comprising a first conductor (312) and a set of further conductors (314). The method (300) comprises providing the first conductor (312) with a first signal transition (210) for signalling the start of a first data communication period (T1); and providing a further conductor (314), after a predefined delay with respect to the provision of the first signal transition (210), with a delayed signal transition (220), the predefined delay defining a first data value. Consequently, the method of the present invention provides a data encoding technique for data communication over a bus that requires less switching activity than other encoding techniques such as pulse width modulation encoding. The present invention further discloses a data communication device (400), a data reception device (500) and a system (300) including these devices, all implementing various aspects of the aforementioned method.

Abstract: A transistor comprises a nanowire (22, 22?) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).