Abstract: Circuit arrangement for detecting a power down situation of a second voltage comprising a first conductor, adapted the be connected to a first voltage, a second conductor, adapted the be connected to a reference voltage, an input node, adapted the be connected to the second voltage, and two output nodes, a first output node and a second output node. The output nodes are interconnected in such a manner, that (a) when the second voltage is higher than the reference voltage, the first output node is at the first voltage level and the second output node is at the reference voltage level, and (b) when the second voltage is equal to the reference voltage, the first output node is at the reference voltage level and the second output node is at the first voltage level.

Abstract: A data communication system, comprising at least three signal conductors and a first and a second power supply terminal, for supplying currents of mutually opposite direction to the signal conductors respectively. A driver circuit establishes respective combinations of currents through the signal conductors from a selectable set of combinations, which includes combinations with currents from the first supply terminal and to the second supply terminal, so that a sum of the currents through the signal conductors substantially has a same value for each combination and at least one of the conductors in operation does not merely function in a differential-pair relation with another one of the conductors, the driver circuit determining which of the combinations from the set are established depending on information to be transmitted.

Abstract: In transmission systems using digital video broadcasting standards for handheld terminals data is transmitted in bursts. A decoder unit (25) is provided to correct errors in the data. An error amount determination unit (30) is provided to determine, when the amount of error correction data for error correction is sufficient for a successful error correction. Therefore, in the average, power consumption of the device (1) may be reduced by an early receiver front-end switch-off.

Abstract: Processing assembly comprising a processing chamber (2) adapted for receiving at least one wafer (5) to be processed, the processing assembly (1) further being provided with a pump (3) being connectable in fluid connection with the processing chamber (2) for maintaining the pressure in the processing chamber (2) in a low pressure range during processing, wherein the processing assembly (1) is provided with a second pump (4) being connectable in fluid connection with the processing chamber (2) for lowering the pressure from a relatively high pressure, e.g. atmospheric pressure, to the low pressure range, wherein gas flow in the processing chamber (2) during lowering the pressure has a constant value. The invention further relates to a method for processing a wafer (5) in such a processing assembly (1).

Abstract: A local area network is provided where an OFDM station and DSSS/CCK station coexist. During a contention-free period both stations operate under the point coordination function rules as defined in the IEEE 802.11 specification. Both stations transmit data when polled by the access point. The contention-free period comprises a sub-contention period during which only the OFDM station communicate. During the sub-contention period the OFDM station operates under the distributed coordination function while the DSSS/CCK station waits to be polled by the access point before starting to communicate.

Abstract: Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers (120) are coupled to the plurality of execution units (160) via distribution means (140). Distribution means (140) have a plurality of dispatch units (144) coupled to the plurality of execution units (160) and a reroutable network, e.g. a data communication bus (142), coupling the plurality of execution units (120) to the plurality of dispatch units (144). The data communication bus (142) is controlled by control unit (148). Dispatch units (144) are arranged to detect dedicated instructions in the instruction flow, which signal the beginning of an inactive period of an execution unit (160a, 160b, 160c, 160d) in the plurality of execution units (160).

Abstract: A display device (1) comprising: a liquid crystal display (2) having pixels (8) which are arranged in columns C and rows R; and a gate driving arrangement (4) for activating the pixels (8) of rows (R) in dependence on a row scanning scheme; a source driving arrangement (3) for providing column voltages representing the respective image data, a number of buffers (40) depending on the number of grey levels for supplying the respective voltage levels to the columns (C), a switching unit (31) for selecting a voltage level which corresponds to the grey level to be displayed; and a control unit (32) for controlling the buffers (40). For reducing the power consumption, an analyzing unit (39) is provided which analyzes the image data to be displayed such that the control unit (32) can determine the number of required buffers in dependence on the number of grey levels to be displayed and can switch off any unused buffers.

Abstract: The present invention relates to a frequency-independent voltage divider in which a compensation structure (10) for compensating a distributed parasitic capacitance of a resistor arrangement (20) is arranged between the resistor arrangement (20) and a substrate (50). Thereby, the compensation structure (10) shields the resistor arrangement (20) partly from the substrate (50), and thus shields the parasitic capacitance. This allows for an improved compensation.

Abstract: A metallization structure in a multilayer stack, which is arranged at a distance from a ground electrode, is characterized in that the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel with the ground electrode at a distance h1, and in that formula (I) where w is the width of the line.

Abstract: Present invention relates to an electrostatic discharge protection circuit for a transistor circuit having electrostatic discharge protection circuits coupled to an input and to an output terminal. The protection circuits comprise delay means having a predetermined delay time and switchable connecting means connected between said input terminal and a control terminal of said transistor circuit. The delay means are configured for activating said switchable connecting means for said predetermined delay time in response to an electrostatic discharge at said input terminal.

Abstract: The invention relates to a Magnetic memory system (1, 20) which comprises an information layer (13) and a sensor (2, 22) for cooperating with the information layer (13). The information layer (13) comprises a pattern of magnetic bits (4a, 4b, 4c, 4d, 24a, 24c, 24d) which constitutes an array of bit locations. A bit magnetic field (3a, 3b, 3c, 3d) at a bit location represents a logical value (LO, L1/2, L1). The sensor (2, 22) comprises a magnetoresistive element (6, 26) comprising a fixed magnetic layer (7) and a free magnetic layer (8). The free magnetic layer (8) has a magnetization axis (10) along which the free magnetic layer retains a free magnetization direction (1 Ib, 1 Ic, 21b, 21c).

Abstract: The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.

Abstract: In a circuit (3) for a data carrier (1), which data carrier (1) comprise a sensor (2) that is designed for providing a sensor signal (SS) that represents an environment parameter and a communication element (CM) that is designed for the contact-less communication with an interrogator station, first connection elements for connecting the circuit (3) to the communication element (CM) and second connection elements for establishing an electronic connection of the circuit (3) to the sensor (2) are provided, wherein the second connection elements are realized by the first connection elements and wherein the circuit (3) comprises a sensor signal processing stage (11A) designed for receiving said sensor signal (SS) via the first connection element and for processing said received sensor signal (SS).

Abstract: An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.

Abstract: The present invention discloses a method and apparatus for implementing matched filter in a system using QPSK modulation. In the present invention, a multiplier is changed as a multiplexer by using the characteristic of the pilot sequence (or training sequence) so as to implement the matched filter.

Abstract: An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two processors 310, 314 from racing to access the same system resources in their respective interrupt service routines.

Abstract: A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.

Abstract: An antenna structure (106) comprising a first electrically conductive element (102) having a first end and a second end, a second electrically conductive element (103) having a first end and a second end, and a coupling structure (104) short-circuiting the first electrically conductive element (102) with the second electrically conductive element (103) by means of electrically connecting the electrically conductive elements (102, 103) at positions between the first and the second ends, wherein an integrated circuit (105) is connectable between the first end of the first electrically conductive element (102) and the first end of the second electrically conductive element (103).

Abstract: A moisture sensor includes interdigitated first and second electrodes formed in trenches 26. A porous low-k dielectric 20 is provided between the electrodes. The electrodes are of Cu 30 surrounded by a barrier layer 28,32 to protect the Cu from corrosion. TiN may be used as barrier layer 28 and selectively deposited barrier material such as CoWB, MoWB or NiMoP as barrier layer 32.

Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.