Abstract: An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IP1-IP5) to enable a communication between the processing modules (IP1-IP5). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IP1-IP5). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (TO-T4) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (TO-T4) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (TO-T4).

Abstract: An electronic circuit contains a driver circuit (12) with an output coupled to a digital communication conductor (14), for driving changes of a potential at the digital communication conductor (14) to and from a digital signal level. The driver circuit (12) comprises a control circuit (120), to generate selection signals that select increasingly stronger drive strengths and increasingly weaker drive strengths during changes to and from the digital level respectively. A controllable current supply circuit (122, 124), has a current control input coupled to the control circuit (120) for receiving the selection signals and a current supply output coupled to the digital communtication conductor (14). A detector circuit (126) has an input coupled to the digital communtication conductor (14) and an output coupled to the control circuit (120), and arranged to detect whether a potential at the digital communication conductor (12) has reached a required range.

Abstract: In order to provide a resonator structure (100) in particular a bulk-acoustic-wave (BAW) resonator, such as a film BAW resonator (FBAR) or a solidly-mounted BAW resonator (SBAR), comprising at least one substrate (10); at least one reflector layer (20) applied or deposited on the substrate (10); at least one bottom electrode layer (30), in particular bottom electrode, applied or deposited on the reflector layer (20); at least one piezoelectric layer (40), in particular C-axis normal piezoelectric layer, applied or deposited on the bottom electrode layer (30); at least one top electrode layer (50), in particular top electrode, applied or deposited on the bottom electrode layer (30) and/or on the piezoelectric layer (40) such that the piezoelectric layer (40) is in between the bottom electrode layer (30) and the top electrode layer (50), it is proposed that at least one dielectric layer (63, 65) applied or deposited in and/or on at least one space in at least one region of non-overlap between the bottom electro

Abstract: A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).

Abstract: A hardware-based method and system classifies and processes data sets according to a set of rules. In one aspect of the invention, the operations associated with data set analysis and classification are offloaded from an interface processor to one or more embedded processors operating in parallel with the interface processor. A set of rules for classifying a data set is represented by instruction sequences stored in the embedded processors' memory. The embedded processors include data set parser logic to decompose data sets into relevant units and rules engine logic for executing the sequence of instructions to determine the classification of data sets. The rules engine logic returns the results of classifying the data sets to the interface processor.

Abstract: The spatial light modulator device (SLM) for providing a spatial light pattern which is alterable in response to an electric signal comprises a first modulator element (ME1) and a second modulator element (ME2). The first light beam (LB1) processed by the first modulator element (ME1) and the second light beam (LB2) processed by the second modulator element (ME2) can be superimposed for forming the spatial light pattern. In this way a defect in the first modulator element (ME1) can be compensated a corresponding pixel of the second modulator element (ME2). The spatial light pattern provided by the first modulator element (ME1) and the second modulator element (ME2) are complementary and combine to the desired spatial light pattern. The spatial light modulator device (SLM) may be used in a lithography apparatus (LA) or a display device (DD).

Abstract: A high voltage asymmetric semiconductor device (20) that includes a shallow trench isolation (STI) region (22) that forms a dielectric between a drain (34) and a gate (36) to allow for high voltage operation, wherein the STI region includes a lower corner (24) that is shaped, e.g. rounded, to reduce an impact ionization rate. Exemplarity the shaped corner terminates on a (111) crystalline plane facet.

Abstract: In order to provide an interface circuit (100; 100?) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100?), in particular the input of the interface circuit (100; 100?), can be provided with, and/or to the data signals (D; R, G, B).

Abstract: A system includes a task scheduler (301) comprising a task execution schedule (101) for a plurality of tasks to be executed on a plurality of cache lines in a cache memory. The system also includes a cache controller logic (303) having a voltage scalar register (305). The voltage scalar register (305) is updated by the task scheduler with a task identifier (204) of a next task to be executed. The system has a voltage scalar (304), wherein the voltage scalar (304) selects one or more cache lines to operate in a low power mode based on the task execution schedule (101). The task execution schedule (101) is stored in a look up table.

Abstract: A compressed data stream modifier 270 is disclosed. The stream modifier modifies an input data stream that may comprise audio and video data streams conforming to any one of the well-known video compression standards, for example, MPEG or AVC. The input stream is first de-multiplexed to obtain a single video elementary stream. The video elementary stream is then decoded by means of a variable-length decoder and provided to the data stream modifier. A decoding complexity of each frame is estimated by an estimator 210 and provided to a controller 250. The controller selects a number of regions from each frame based on some psycho-visual criteria, such that a method of modification of these regions can bring the decoding complexity within an available capacity at a decoder. An efficient means of adapting a decoding complexity to an available capacity is thus obtained.

Abstract: The present invention discloses a vertical phase-change-memory (PCM) cell, comprising a stack of a bottom electrode (5) contacting a first layer of phase change material (14), a dielectric layer (12) having an opening (13), a second layer of phase change material (6) in contact with the first layer of phase change material through the opening in the dielectric layer and a top electrode (7) contacting this second layer of phase change material.

Abstract: A method for analyzing an integrated circuit (IC) comprising a plurality of semiconductor devices is disclosed. The method comprises the steps of forming a diffraction lens (100) comprising a plurality of concentric diffraction zones (110) in a first area of a further surface opposite to the first surface of the substrate (10), and a further step of optically accessing a subset (30) of the plurality of semiconductor devices (20) through the diffraction lens (100). Due to the fact that a diffraction lens (100) can be implemented at submicron sizes, the lens (100) can be formed more cheaply than a refraction lens, which usually is several microns deep. Moreover, the lens (100) can be easily polished off the substrate (10), which facilitates repeated relocation of the lens (100) on the substrate (10), thus improving the chance of optically detecting a fault inside the IC.

Abstract: A switched mode power converter is provided which includes a transformer (2) having a primary winding (2a) and at least one secondary winding (2b); a primary side active switch device (S1) coupled to the primary winding for selectively applying an input voltage to the primary winding; and a secondary side rectifier circuit including an output filter (6, 12) coupled to the at least one secondary winding (2), and first and second active switch devices (16, 14) coupled between the at least one secondary winding (2b) and the output filter. The switch devices are arranged such that each one is operable independently of the other to block current between the at least one secondary winding and the output filter in an opposite direction to the other. This facilitates better regulation of the converter and avoids the occurrence of voltage spikes encountered in existing configurations.

Abstract: Systems involving temperature compensation of voltage controlled oscillators are provided. In this regard, a representative system incorporates: a voltage controlled oscillator (VCO) having a tuning port and a phase-locked loop (PLL); and a temperature dependent voltage source. The VCO selectively exhibits one of a coarse tuning mode in which the temperature dependent voltage source is electrically connected to the VCO tuning port, and a locked mode in which the temperature dependent voltage source is not electrically connected to the VCO tuning port such that the PLL controls the frequency of the VCO.

Abstract: The invention relates to a dual-band antenna for preferable operation in the GSM and DCS frequency range. The dual-band antenna at the same time has the functionality of a diplexer. This makes it possible to produce wireless communication devices with one component less, which in turn reduces weight and production cost.

Abstract: A logic circuit having structure for performing the AES Rijndael MixColumns transform exploits the relationship between each successive row of the transform matrix and its preceding row. Multiplication of an (m.times.n) matrix by a (1.times.n) or by a (m.times.1) matrix is performed, where m is a number of rows and n is a number of columns, and where each successive row, m, of n elements is a predetermined row permutation of a preceding row, includes: n multiplication circuits; n logic circuits; n registers for receiving logical output from the logic circuits; feedback logic for routing contents of each register to a selected one of inputs of the logic circuits in accordance with a feedback plan that corresponds to the relationship between successive matrix rows; and a control unit for successively providing as input to each of the n multiplication circuits each element in the (1.times.n) or (m.times.1) matrix.

Abstract: A method and a test arrangement for testing an SRAM having a first cell and a second cell coupled between a pair of bitlines is disclosed. In a first step, a data value is stored in the first cell being the cell under test (CUT), and its complement is stored in a second cell, being the reference cell. Next, the bitlines are precharged to a predefined voltage. Subsequently, the wordline of the reference cell is enabled for a predefined time period, for instance by providing the wordline with a number of voltage pulses. This causes a drop in voltage of the bitline coupled to the logic ‘0’ node of the reference cell. In a subsequent step, the wordline of the CUT is enabled, which exposes the CUT to the bitline with the reduced voltage. This is equivalent to weakly overwriting the CUT. Finally, the data value in the CUT is evaluated. If the data value has flipped, the CUT is a weak cell. Cells with varying levels of weakness can be detected by varying the reduced voltage on the aforementioned bitline.

Abstract: A plurality of processors (10) in a multiprocessor circuit is coupled to a plurality of independently addressable memory banks (12) via a connection circuit (14). The connection circuit is arranged to forward addresses from a combination of the processors (10) to addressing inputs of memory banks (12) selected by the addresses. The connection circuit (14) provides for a conflict resolution scheme wherein at least one of the processors (10) is associated with an associated one of the memory banks (12) as an associated processor. The connection circuit (14) guarantees the associated processor a higher minimum guaranteed access frequency to said associated one of the memory banks (12) than to a further one of the memory banks (12) other than the associated one of the memory banks (12).

Abstract: There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapour deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.