Abstract: A plurality of processors (10) in a multiprocessor circuit is coupled to a plurality of independently addressable memory banks (12) via a connection circuit (14). The connection circuit is arranged to forward addresses from a combination of the processors (10) to addressing inputs of memory banks (12) selected by the addresses. The connection circuit (14) provides for a conflict resolution scheme wherein at least one of the processors (10) is associated with an associated one of the memory banks (12) as an associated processor. The connection circuit (14) guarantees the associated processor a higher minimum guaranteed access frequency to said associated one of the memory banks (12) than to a further one of the memory banks (12) other than the associated one of the memory banks (12).

Abstract: An adapter (3, 3?, 3?) for a loudspeaker (2) is disclosed, wherein the loudspeaker (2) is provided to be used in free space. The adapter (3) comprises means to provide an acoustic impedance on the backside (b) of the loudspeaker (2) in such a way, that an adaptation of the loudspeaker function from a free-space operation mode to an on-the-car or in-the-car operation mode is achieved.

Abstract: An electronic quadrature device is provided comprising at least one I signal path (I) and at least one Q signal path (Q); at least one first sigma-delta modulator (DSDMI) and at least one first digital/analog converter unit (DACI) arranged in the at least one I signal path (I); and at least one second sigma-delta modulator (DSDMQ) and at least one second digital/analog converter unit (DACQ) arranged in the at least one Q signal path (Q). The at least one first sigma-delta modulator (DSDMI) is coupled to the at least one second sigma-delta modulator (DSDMQ) via at least one complex signal path (C1-C4) to implement a complex filter.

Abstract: The invention relates to a method and a system for calibrating a transmitting system (1) for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (PHY) and an antenna (3) to a transmission line (4), wherein the physical layer (PHY) comprises a base band controller (5) and a data processing pipeline (6) comprising a plurality of functional blocks (FB1 to FB13), comprising the following steps: setting a calibration control register (R), thereupon, setting the transmitting system (1) to a calibration mode, wherein the transmitting system (1) generates a predetermined number of single test tones (T) and transmits the test tones (T) sequentially, and after transmission of the test tones (T), detecting the returned test tones (T) and measuring their levels, especially their power levels and the spectrum behaviour of the transmission line (4).

Abstract: A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self-aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well controlled.

Abstract: The invention relates to a method for accessing matrix elements, wherein accesses to two matrix elements that are adjacent in a row or in a column of a matrix and that are each specified by a respective relative address (ar, ac) are performed for the first of said elements in a first memory block (Bp1) using a first local address (a?1) and for the second of said elements in a different second memory block (Bp2) using a second local address (a?2)

Abstract: A multiprocessor system-on-chip 102 with dynamic adaptive power management for execution of data-dependent applications comprises strategically placed performance counters to collect run-time performance requirements of tasks. A power manager 130 issues DVS 132, DFS 134, time-out 136, and other controls to the various system resources being monitored. As the tasks execute during run-time, the quality of the match between the task and the resource it was scheduled to is analyzed. More accurate power controls and schedules are then made available and stored in a performance requirements table. The power-management is therefore adaptive and dynamic. During a static analysis phase, applications and tasks that can be pre-characterized for their performance requirements are profiled and pre-loaded as initial starting points for correction during run-time.

Abstract: The invention relates to a receiver (1) comprising an amplifier (31-34) for amplifying an antenna signal, which amplifier (31-34) comprises an amplifier input (11a) and an amplifier output (12a, 12b), the amplifier input (11a) being a single ended input for receiving the antenna signal, the amplifier output (12a, 12b) being a differential output, and the amplifier (31-34) comprising a circuit (54) for compensating a series input impedance of the amplifier (31-34).

Abstract: A method of making a semiconductor device includes forming shallow trench isolation structures (14) in a semiconductor device layer. The shallow trench isolation structures are U- or O-shaped enclosing field regions (28) formed of the semiconductor device layer which is doped and/or suicided to be conducting. The semiconductor device may include an extended drain region (50) or drift region and a drain region (42). An insulated gate (26) may be provided over the body region. A source region (34, 40) may be shaped to have a deep source region (40) and a shallow source region (34). A contact region (60) of the same conductivity type as the body may be provided adjacent to the deep source region (40). The body extends under the shallow source region (34) to contact the contact region (60).

Abstract: In the case of a data carrier (1) or an integrated circuit (5) for the data carrier (1), an ESD protection circuit (8) is formed by means of a series connection (9) comprising a first protection diode (10) and a protection stage (11) together with a second protection diode connected in parallel with the series connection (9), and a rectifier circuit (13) connected with the ESD protection circuit (8) is provided, which comprises a rectifier diode connected in parallel with the ESD protection circuit (8), wherein the rectifier diode takes the form of a Schottky diode (21) with a parasitic p/n junction (26) and wherein the Schottky diode (21) with the parasitic p/n junction (26) forms the second protection diode of the ESD protection circuit (8).

Abstract: The invention relates to an arrangement with two piezoelectric layers (2, 5) and to a method of operating the arrangement as a filter. One (2) of the two piezoelectric layers (2, 5) in the arrangement is situated between an electrode (3) and a middle electrode (4), and the other one (5) of the two piezoelectric layers (2, 5) is positioned between another electrode (6) and said middle electrode (4) such that a bulk acoustic wave resonator is formed. The one and the other electrode (3, 6) and the middle electrode (4) are connected to circuitry means for applying high-frequency signals to at least one of the two piezoelectric layers (2, 5) such that the bulk acoustic wave resonator has at least one resonance frequency when the circuitry means are in one switching state, and that the bulk acoustic wave resonator has at least one other resonance frequency different from the at least one resonance frequency when the circuitry means are in another switching state.

Abstract: The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal (15) which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.

Abstract: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

Abstract: The present invention relates to a simple and small-sized circuit configuration (10) for significantly reducing resettling time of a peak or zero current comparator. This circuit configuration (10) provides the comparator input stage with an alternative current path at the comparator input submitted to a large voltage variation able to disturb the DC-settings. This circuit configuration (10) comprises a pair of small transistors (P3, P4) coupled to a differential pair of transistors (N1, N2) of the comparator input stage and having a polarity different from said pair of transistors (P3, P4). The gates of the transistors P3 and P4 share a common terminal connected to said comparator input. The currents and voltages across the comparator are always maintained close to the normal DC-setting values during the voltage transition phase. This circuit configuration (10) can be used in any current comparator for detecting a peak or a zero current, in particular, in DC-DC converters based on a switched operating mode.

Abstract: The present invention discloses a moving system (3) for a piezoelectric speaker (1), comprising a membrane (4) and a piezoelectric layer (5) attached thereto, wherein a movement of the moving system (3) in a main direction (MD) is substantially caused by dilatation/contraction of the piezoelectric layer (5) transverse to said main direction (MD). Accordingly, there is no translatory movement when exciting the moving system (3), but only a bending movement. To provide an advantageous frequency response of the moving system (3), it is built up asymmetrically with respect to the moving characteristics. Accordingly, the modes are frequency shifted on the one hand and of less influence on the other. Hence, the frequency response of an inventive speaker (1) has less elevations and depressions in the frequency response. The concrete design of a moving system (3) is preferably done by the use of a computer simulation based on a finite elements method.

Abstract: Devices (1) comprising sensor arrangements (2) for providing first field information defining at least parts of first fields and for providing second field information defining first parts of second fields are provided with estimators (4) for estimating second parts of the second fields as functions of mixtures of the first and second field information, to become more reliable and user friendly. The fields may be earth gravitational fields and/or earth magnetic fields and/or further fields. The mixtures comprise dot products of the first and second fields and/or first products of first components of the first and second fields in first directions and/or second products of second components of the first and second fields in second directions. The second parts of the second field comprise third components of the second field in third directions. The estimators (4) can further estimate third components of the first field in third directions as further functions of the first field information.

Abstract: The present invention relates to an electronic device (300) comprising at least one trench capacitor (302) that can also take the form of an inverse structure, a pillar capacitor. An alternating layer sequence (308) of at least two dielectric layers (312, 316) and at least two electrically conductive layers (314, 318) is provided in the trench capacitor or on the pillar capacitor, such that the at least two electrically conductive layers are electrically isolated from each other and from the substrate by respective ones of the at least two dielectric layers. A set of internal contact pads (332, 334, 340) is provided, and each internal contact pad is connected with a respective one of the electrically conductive layers or with the substrate. By providing an individual internal contact pad for each of the electrically conductive layers, a range of switching opportunities is opened up that allows tuning the specific capacitance of the capacitor to a desired value.

Abstract: The present invention relates to a capacitor device (500), an electronic circuit comprising a capacitor device, to an electronic component, and to a method of forming a capacitor device. In the capacitor device of the invention, a current-path region (530) extends from one of two trench capacitor electrodes to a respective contact structure (520). The current-path region of the capacitor device of the invention is obtainable by thinning the substrate from an original substrate thickness down to reduced substrate thickness either in a lateral substrate portion containing the capacitor region or over the complete lateral extension of the substrate before forming the first and second contact structures. The capacitor device of the invention has the advantage of exhibiting a reduced impedance in the current-path region. This reduced impedance implies a low self-inductance and self-resistance that is caused by the current-path region of the capacitor device.

Abstract: A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1,C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2,C1) by means of a command designating the second address.

Abstract: An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request input (22) and an acknowledgement input (24). The protocol used has a single signal, output on the combined acknowledgement and request output (20) of a stage (30), that functions both as a request to the next stage (32) and an acknowledgement to the previous stage (34).