Patents Assigned to RENESAS
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Patent number: 11652100Abstract: A semiconductor device has a silicon film for a diode formed on a semiconductor substrate via an insulating film, and first and second wirings formed on an upper layer of the silicon film. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring.Type: GrantFiled: May 7, 2021Date of Patent: May 16, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyoshi Kudou, Taro Moriya, Satoshi Uchiya
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Patent number: 11652072Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.Type: GrantFiled: April 8, 2021Date of Patent: May 16, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Tonegawa, Hiroshi Inagawa
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Publication number: 20230147156Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.Type: ApplicationFiled: November 9, 2022Publication date: May 11, 2023Applicant: Renesas Electronics CorporationInventors: Pratama FAJARMEGA, Tatsuo NISHINO, Takehiro SHIMIZU
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Publication number: 20230146600Abstract: Systems, apparatuses, and methods for detecting a foreign object on a wireless power charging region are described. A circuit can detect an object inductively coupled to a wireless power transmitter. The circuit can further measure an input parameter prior to a power transfer stage, the input parameter can be one of an input current and an input power. The circuit can further compare the measured input parameter with a predetermined value. The circuit can further determine whether the object is a foreign object or the wireless power receiver based on a result of the comparison between the measured input parameter with the predetermined value.Type: ApplicationFiled: August 9, 2022Publication date: May 11, 2023Applicant: Renesas Electronics America Inc.Inventors: Chan Young Jeong, Tao Qi, Young Chul Ryu, Kwangmuk Choi, Pooja Agrawal, Krishal Jaswantsinh Solanki, Adnan Dzebic
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Patent number: 11646731Abstract: To provide a technique for detecting a low voltage of a power-on reset circuit. A semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor formed by connecting a plurality of bipolar transistors in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator.Type: GrantFiled: December 23, 2021Date of Patent: May 9, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Issei Kashima, Atsushi Tsuda
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Patent number: 11646376Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.Type: GrantFiled: September 20, 2021Date of Patent: May 9, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Eiji Tsukuda, Katsumi Eikyu
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Publication number: 20230138391Abstract: A semiconductor device includes a digital-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-analog converter to test the digital-analog converter. The test circuit includes: a charge information holding circuit that holds, as differential charge information, a difference value between a first charge according to a first current and a second charge according to a second current by at least one or more current cells among the plurality of current cells; a reference voltage generation circuit that generates a reference voltage to be comparative object; and a comparison circuit that compares a determination voltage according to the differential charge information and the reference voltage to output a comparison result.Type: ApplicationFiled: November 1, 2022Publication date: May 4, 2023Applicant: Renesas Electronics CorporationInventors: Wataru SAITO, Fukashi MORISHITA
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Publication number: 20230136373Abstract: A method for dynamic error compensation of a position sensor and a position sensor are disclosed. In the method, a calculated speed of a moving target for a current determined position is compared to a calculated running average of the speed of the moving target over a certain number of determined positions and if the calculated speed of the moving target for the current position is within a first window around the calculated running average of the speed of the moving target over the certain number of determined positions the dynamic angle error is not re-calculated for the current determined position, and/or if the calculated speed of the moving target for the current determined position exceeds a second window the previously calculated running average is deleted and the calculation of the running average of the speed of the moving target over a certain number of determined positions is restarted.Type: ApplicationFiled: October 20, 2022Publication date: May 4, 2023Applicant: Renesas Electronics America Inc.Inventor: Ruggero LEONCAVALLO
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Publication number: 20230128387Abstract: Systems and methods for amplifying a signal is described. A circuit may convert an input radio frequency (RF) signal into a first RF signal with power level matching a power capacity of a first transistor of a first size in a carrier amplifier stage, a second RF signal with power level matching a power capacity of a second transistor of the first size in a peaking amplifier stage, and a third RF signal with third power level matching a power capacity of a third transistor of a second size in another peaking amplifier stage. The circuit may amplify the first, second, and third RF signals to generate first, second, and third amplified RF signals, respectively. The circuit may combine the first, second, and third amplified RF signals, into an output RF signal that is an amplified version of the input RF signal.Type: ApplicationFiled: October 27, 2021Publication date: April 27, 2023Applicant: Renesas Electronics America Inc.Inventors: Hussain Hasanali Ladhani, Ramanujam Srinidhi Embar, Michael Guyonnet, Tushar Sharma, Shishir Ramasare Shukla
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Publication number: 20230129498Abstract: Methods, systems, and apparatuses for a single edge nibble transmission (SENT) multi-transmission mode are described. In an example, a system can include a transmitter and a receiver connected to one another. The transmitter may encode an identifier of a device in a synchronization nibble of a SENT signal. The transmitter may transmit the SENT signal with the encoded identifier to the receiver. The receiver may receive the SENT signal from the transmitter. The receiver may decode the identifier of the device from the synchronization nibble of the SENT signal to identify the device.Type: ApplicationFiled: October 25, 2021Publication date: April 27, 2023Applicant: Renesas Electronics America Inc.Inventor: Steffen Bender
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Publication number: 20230119255Abstract: An integrated circuit includes a safety processor and a secure computing module including a secure processor, first and second cryptographic units for encrypting and decrypting data, and first and second data transfer units for transferring data between a memory and the first and second cryptographic units respectively. The first cryptographic unit and the first data transfer unit provide a first cryptographic data handling system and the second cryptographic unit and the second data transfer unit provide a second cryptographic data handling system. The secure computing module includes selector circuitry for selectively coupling and uncoupling the first and second cryptographic units in response to control signals from a switch. In a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other. In a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy.Type: ApplicationFiled: October 7, 2022Publication date: April 20, 2023Applicant: Renesas Electronics CorporationInventor: Mohamed SOUBHI
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Publication number: 20230120972Abstract: Methods and systems for determining a position of a structure using inductive position sensing are described. In an example, a processor may receive a plurality of data points representing a plurality of voltages. The plurality of voltages may be generated by a plurality of sensor coils based on a magnetic flux field. The magnetic flux field may be generated by a plurality of driver coils, and the plurality of voltages may vary with changes in the magnetic flux field. The processor may calibrate the plurality of data points to generate a plurality of calibrated data points. The processor may filter the plurality of calibrated data points. The processor may estimate a position of the structure based on the filtered calibrated data points, where the position of the structure may indicate a size of a size changing device.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Applicant: Renesas Electronics America Inc.Inventors: Damla S. Acar, Pooja Agrawal, Ashley M. De Wolfe, Gustavo James Mehas, Nicholaus W. Smith
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Publication number: 20230118432Abstract: A method, apparatus and non-transitory computer-readable medium of regulating current within a battery charging circuit. The apparatus including a first current sense resistor configured to sense a first current value at a first port, a second current sensor resistor configured to sense a battery discharge current value output from a battery, and a processor configured to, in response to a short circuit or malfunction at the first current sense resistor, use the battery discharge current value to determine an output current limit and to limit the current at the first port according to the output current limit.Type: ApplicationFiled: October 15, 2021Publication date: April 20, 2023Applicant: Renesas Electronics America Inc.Inventors: Shahriar Jalal NIBIR, Yen-Mo CHEN, Sungkeun LIM
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Publication number: 20230121953Abstract: Apparatuses and methods for regulating a system rail voltage of a battery charger is described. An integrated circuit can be configured to detect a condition that requires an activation of a trickle charge mode of a battery charger. The integrated circuit can, in response to the detection, set a reference voltage to an intermediate voltage level. The reference voltage can control a system rail voltage of the battery charger, and the intermediate voltage level can be greater than a minimum of the system rail voltage. The integrated circuit can reduce the reference voltage from the intermediate voltage level to the minimum system rail voltage to regulate the system rail voltage at a predefined rate.Type: ApplicationFiled: April 22, 2022Publication date: April 20, 2023Applicant: Renesas Electronics America Inc.Inventors: Mehul Dilip SHAH, Sivaprakash KANNAN, Yang LI, Xiwen ZHANG
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Patent number: 11630270Abstract: A semiconductor device includes a cladding layer and a first optical waveguide. The first optical waveguide is formed on the first cladding layer. An end surface of the first optical waveguide is inclined relative to a vertical line perpendicular to an upper surface of the cladding layer.Type: GrantFiled: March 6, 2020Date of Patent: April 18, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuya Iida, Yasutaka Nakashiba
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Patent number: 11631764Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.Type: GrantFiled: October 1, 2020Date of Patent: April 18, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Hisada, Koichi Arai, Hironobu Miyamoto
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Patent number: 11632003Abstract: A current sensing circuit and a minimum operating frequency for a wireless power transmission system is presented. A method of measuring current through a wireless power transmit coil, includes receiving a signal from a switching circuit into a sampling circuit; filtering the sampled signal from the sampling circuit; biasing the filtered sampled signal, wherein the biasing occurs only when the sampling circuit is active; and amplifying the biased signal to provide a transmit coil current signal. A method of measuring current through a wireless power transmit coil, includes receiving a signal from a switching circuit into a sampling circuit; filtering the sampled signal from the sampling circuit; biasing the filtered sampled signal, wherein the biasing occurs only when the sampling circuit is active; and amplifying the biased signal to provide a transmit coil current signal.Type: GrantFiled: June 8, 2022Date of Patent: April 18, 2023Assignee: Renesas Electronics America Inc.Inventor: Gustavo Mehas
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Publication number: 20230110907Abstract: A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.Type: ApplicationFiled: October 3, 2022Publication date: April 13, 2023Applicant: Renesas Electronics CorporationInventors: Thorsten HOFFLEIT, Christian MARDMÖLLER
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Publication number: 20230116552Abstract: A position sensor, wherein the position sensor detects the movement of a target relative to a sine receiver coil and a cosine receiver coil and generates a corresponding sine signal and a corresponding cosine signal, and a method for error detection of a position sensor.Type: ApplicationFiled: October 3, 2022Publication date: April 13, 2023Applicant: Renesas Electronics America Inc.Inventors: Gentjan Qama, Jürgen Peter Kernhof, Angel Karachomakov, Andreas Leo Buchinger, Thomas Oswald
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Patent number: 11626374Abstract: A semiconductor device includes a wiring substrate including a first wiring layer. The first wiring layer includes a first wiring pattern which is a transmission path of a first signal, a second wiring pattern which is a transmission path of a second signal and which is arranged next to one side of the first wiring pattern, and a third wiring pattern which is a transmission path of a third signal and which is arranged next to the other side of the first wiring pattern. A wiring pattern group including the first through third wiring patterns has: a first portion in which wiring widths of the first through third wiring patterns are equal to each other; and a second portion in which the wiring width of the first wiring pattern is larger than the wiring width of each of the second and third wiring patterns.Type: GrantFiled: November 5, 2021Date of Patent: April 11, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuaki Tsukuda