Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

Abstract: A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

Abstract: A semiconductor device capable of performing filter processing while suppressing an increase in processing time is provided. The semiconductor device includes a microcontroller. The microcontroller comprises a CPU, a memory and a CAN-controller. The memory stores software. The CPU executes the software stored in the memory. The CAN controller is configured to add label information to the message information. The CAN routing software stored in the memory implements a filtering function for performing a filter processing for determining whether or not to route the message information by using the label information.

Abstract: A semiconductor device includes an external terminal, an input buffer having an input terminal connected to the external terminal, a voltage generating circuit configured to generate a test voltage supplied to the input terminal, and a control circuit configured to determine whether the input buffer is deteriorated based on the test voltage supplied to the input terminal and an output level of the input buffer responding to the test voltage.

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

Abstract: A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.

Abstract: To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.

Abstract: A semiconductor device includes a first transistor that flows a current to a load, a current generation circuit that outputs a current corresponding to a power consumption of the first transistor, a temperature sensor, a resistor-capacitor network coupled between the current generation circuit and the temperature sensor and an overheat detection circuit coupled to a connection point of the current generation circuit and the resistor-capacitor network, wherein the resistor-capacitor network comprises a resistor and a capacitor corresponding to a thermal resistance and a thermal capacitance between the first transistor and the temperature sensor.

Abstract: To provide a semiconductor device with a digital-controlled DC-DC converter capable of stable feedback operation while minimizing area, the semiconductor device includes a DC-DC converter whose characteristic is determined by the control parameter, a flash memory and a processor that controls the flash memory, both of which operate at a power supply based on the output of the DC-DC converter. The control parameter is stored in the flash memory, and the control parameter is read out from the flash memory and set in the DC-DC converter by the processor while the DC-DC converter is operating.

Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

Abstract: A manufacturing method of a semiconductor device includes: (a) forming a gate structure for a control gate electrode on a semiconductor substrate; (b) forming a charge storage film so as to cover a first side surface, a second side surface, and an upper surface of the gate structure; (c) forming a conductive film for a memory gate electrode on the charge storage film; (d) removing a part of the charge storage film and a part of the conductive film such that the charge storage film and the conductive film remain in this order on the first side surface and the second side surface of the gate structure, thereby forming the memory gate electrode; and (e) removing apart of the gate structure separate from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure.

Abstract: A phase locking circuit includes: a phase comparator; a pulse generation circuit; a charge pump circuit; a loop filter circuit; and a voltage-controlled oscillator. The phase comparator samples a first level in synchronization with a received reference clock, and generates a first signal to be initialized to a second level that is different from the first level by using a feedback clock. The pulse generation circuit generates a second signal in accordance with the reference clock, and controls a phase of as output signal of the voltage-controlled oscillator to be the feedback clock to have a predetermined value by inputting the first signal and the second signal as a control voltage to the voltage-controlled oscillator through the charge pump circuit and the loop filter circuit.

Abstract: A circuit for use in frame filtering is disclosed. The circuit includes a plurality of comparator units. Each comparator unit configured, in response to receiving at least a part of a data frame, to perform a determination whether data in a portion of the at least part of the data frame matches respective reference data and to provide a result to a comparator unit output based on the determination. The circuit includes a crossbar switch having crossbar inputs coupled to respective comparator unit outputs and configured to provide sets of crossbar switch outputs via configurable interconnects; and a set of result-combining logic units, each result-combining logic unit coupled to a respective set of crossbar switch outputs, and configured to provide a respective logic unit output.

Abstract: Simulator includes a first core unit corresponding to the first simulation model, a second core unit corresponding to the second simulation model, a slave block unit for communicating with one of the first core unit and the second core unit, the first core unit and the second core unit and a simulation control unit for causing either to execute instructions. The first core unit includes a high-speed mode instruction execution control unit that stops executing subsequent instructions in response to a request for switching from the first simulation model to the second simulation model, and a transaction monitor unit that monitors whether or not the transaction processing between the first core unit and the slave block unit has been completed. The simulation control unit causes the second core unit to execute instructions in response to a notification of completion of the transaction processing from the transaction monitor unit.

Abstract: An electronic device capable of reducing a process associated with a radar search is provided. The electronic device DEVa has a transmitting linear array antenna TXA, a receiving linear array antenna RXA, and a control circuit CTLU for controlling the transmitting linear array antenna TXA and the receiving linear array antenna RXA. The transmitting linear array antenna TXA includes a plurality of transmission antennas TXr[1] to TXr[4] arranged along the Z direction, and transmits a transmission wave. The receiving linear array antenna RXA includes a plurality of reception antennas RXr[1] to RXr[4] arranged along an X direction orthogonal to the Z direction, and receives a reflected wave of a transmission wave.

Abstract: Example implementations include a method of pre-bootup fault monitor of a LASER diode driver output, by applying a first power to a pre-bootup fault monitor device, setting a fault condition at the pre-bootup fault monitor device to a no-fault state, initiating the pre-bootup fault monitor device, determining whether a first impedance of driver output satisfies an impedance threshold, and in response to a determination that the first impedance satisfies the impedance threshold, applying a second power to the output device.

Abstract: Methods and apparatuses for regulating a power converter are described. A device comprising a control circuit and a logic circuit can be integrated in a controller coupled to the power converter. The control circuit can generate a constant off-time signal based on a ramp signal and an error signal. The logic circuit can generate a control signal based on the constant off-time signal and a constant on-time signal. The logic circuit can output the control signal to the power converter. In response to an on-time period of the constant off-time signal being less than an on-time period of the constant on-time signal, the control signal can vary according to the constant on-time signal. In response to the on-time period of the constant off-time signal being greater than the on-time period of the constant on-time signal, the control signal can vary according to the constant off-time signal.

Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.

Abstract: Methods and systems for operating a multiphase voltage regulator are described. The multiphase voltage regulator can include a plurality of power stages. A controller can be connected to the plurality of power stages. The controller can detect a number of activated power stages among the plurality of power stages. The controller can adjust a gain of a current sense feedback loop of the controller to control a load-transient response of the multiphase voltage regulator. The adjustment to the gain can be based on the number of activated power stages.