Abstract: Methods and apparatuses for controlling an apparatus comprising a controller integrated in a first slave device. In an example, the controller can detect a sensed current of the first slave device. The controller can receive a voltage signal associated with a second slave device connected to the first slave device. The controller can generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can modulate a pulse width modulation (PWM) signal received by the first slave device using the correction current. The controller can control a power converter using the modulated PWM signal.

Abstract: Methods and apparatuses for signal attenuation is described. In an example, an attenuator can be configured to perform attenuation of signals for an integrated circuit. The attenuator can vary the attenuation with an ambient temperature. The attenuator can further adjust the attenuation based on a control signal applied to the attenuator. The control signal can be based on one or more of a temperature profile of the attenuator and a target gain variation of the integrated circuit.

Abstract: A semiconductor device that can reduce power consumption while improving the accuracy of learning and inference is provided. The semiconductor device is connected to data lines PBL, NBL, and comprises a product operation memory cell 1 for storing data of ternary value and performing a product-sum operation between a stored data and an input data INP and a data in the data lines PBL, NBL.

Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

Abstract: A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

Abstract: A microcontroller includes a CPU and a cryptographic circuit, and when a first program uses the cryptographic circuit, the second program transmits installation information of the first program and encrypted program installation information to the cryptographic circuit. The cryptographic circuit decrypts the encrypted program installation information and compares it with the installation information of the first program. In the case of match, the use of the cryptographic circuit by the first program is permitted.

Abstract: In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.

Abstract: It is an object of the present invention to provide a technique for reducing the variation of a bias voltage. An analog-to-digital converter comprises a comparator including a first amplifier and a second amplifier inputted one output of the first amplifier. The first amplifier is a differential type of amplifier, and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal which changes with a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto zero voltage based on the amplified voltage by an auto zero operation of the first amplifier and includes a self-bias circuit using the auto zero voltage as a bias voltage. The comparator is plural, the comparators are plurality which arranged in a row direction, and outputs a digital value based on an analog voltage inputted to the other input terminal in parallel operation.

Abstract: The present invention relates to a semiconductor device having a first processor element configured to receive a first interrupt request signal, a second processor element configured to receive a second interrupt request signal, a first priority determination circuit configured to receive a plurality of interrupt signals and to output the first interrupt request signal to the first processor element, a second priority determination circuit configured to receive the plurality of interrupt signals and to output the second interrupt request signal to the second processor element, a checker circuit configured detect failures of the first priority determination circuit and the second priority determination circuit, and a control circuit configured to select one of the first priority determination circuit or the second priority determination circuit as a circuit to be checked. The control circuit selects the circuit to be checked based on the first interrupt request signal and the second interrupt request signal.

Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

Abstract: According to certain aspects, the present embodiments are directed to techniques for providing the ability to monitor one or more operational parameters of a voltage regulator. In embodiments, the voltage regulator is a multiphase voltage regulator having a plurality of power stages corresponding to each respective phase. In these and other embodiments, the operational parameters include one or both of a phase current and a phase temperature. According to certain additional aspects, the present embodiments provide the ability to monitor the respective phase current output and phase temperature of each phase independently. According to further aspects, this ability to monitor the operational parameters is achieved while minimizing circuit complexity.

Abstract: A semiconductor device includes a transmission control unit which performs transmission processing, an area determination unit which determines whether an own vehicle is located in an intersection area, and an operation mode determination unit which determines either a control mode or a terminal mode as an operation mode of a radio terminal device based on an identification information for identifying a source of a received communication frame, and a determination result by the area determination unit. When the operation mode is determined to be the control mode, the transmission control unit outputs, as transmission data, a communication frame including generated control information. When the operation mode is determined to be the terminal mode, the transmission control unit outputs transmission data in synchronization with the received communication frame.

Abstract: An apparatus includes an amplifier circuit and a protection circuit. The amplifier circuit may be configured to generate an output signal by amplifying an input signal received at an input port. The input signal may be a radio-frequency signal. The protection circuit may be configured to (i) generate a detection signal by detecting when a level of the input signal exceeds a corresponding threshold, where the level is a power level, a voltage level or both, (ii) route the input signal away from the input port of the amplifier circuit and disable the amplifier circuit both in response to the detection signal being continuously active at least a first time duration and (iii) route the input signal to the input port of the amplifier circuit and enable the amplifier circuit both in response to the detection signal being continuously inactive at least a second time duration.

Abstract: A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.

Abstract: The present embodiments relate generally to DC-DC converters and more particularly to a scheme for providing current sharing between parallel converters in a multiphase configuration. In some embodiments, a cycle-by-cycle instant correction to the compensation signal offset is provided based on the current share error between the paralleled converters so as to achieve improved instant current share performance.

Abstract: A solid-state imaging device capable of suppressing variations in reference voltages and improving performance of reference voltages is provided. According to one embodiment, the solid-state imaging device includes a pixel outputting a luminance signal voltage corresponding to an amount of incident light, reference voltages, a reference voltage generation circuit outputting a ramp signal and an inverse ramp signal, and an AD converter, and the AD converter includes a comparator including an amplifier coupled to one input terminal, a reference voltage and an input terminal coupled to each of the ramp signals via a capacitor, and an input terminal coupled to each of the reference voltage and the ramp signal via a capacitor, and a ramp current cancel circuit coupled to each of the reference voltages via a cancel capacitor.

Abstract: To realize a low power consumption and a small area of a network communication system and a semiconductor device for mounting the same. In the processing method of the network router or network communication frame, the received frame is input to the hash generator, to obtain an address based on the resulting hash value, the position of the address in the rule table, stores the rule corresponding to the received frame.

Abstract: A semiconductor device includes a memory, a random number generation circuit, and a control circuit. The memory stores key information, and the random number generation circuit generates first and second random number signals. The control circuit generates sixth and seventh random number signals from the first random number signal and the key information, generates encrypted update data from update data using the seventh random number signal, transmits the first and second random number signals as request signals to an external terminal device, receives, from the external device, first and second response signals as response signals in response to the request signals, generates an eighth random number signal using the first response signal, the second and the sixth random number signals as input signals, and provides the encrypted update data for the external terminal device when the second response signal coincides with the eighth random number signal.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: A power electronic module is provided that includes an electrical connection on opposing surfaces of an electronic component that allows a high current path from a top board to a bottom board through the body of the electronic component thus improving the power electronic module's electrical resistance and reducing the current load on the connector structure which is located between the first substrate and the second substrate. The power electronic module further includes a semiconductor component positioned on an external surface of the top board which allows for thermal contact of the semiconductor component with an external heat sink thus providing an efficient system thermal management via a reduced heat dissipation path. Additional heat dissipation can be obtained by disposing a metallic spacer on the semiconductor component of the power electronic module of the present disclosure.