Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Abstract: A method of over-current protection in a wireless power receiver operating in a high-power mode includes digitally receiving an output current signal, generating an OC INT signal if the output current signal is greater than a current limit value, and if the OC INT signal is generated, transmitting Count A number of End Power Transfer (EPT) packets. If wireless power transmission has not stopped, transmitting Count C number of Control Error Packets (CEPs) with Value B. If wireless power transmission has not reduced such that the output current IL is below the current limit value, then enabling an LDO current limit circuit in a power block of the wireless power receiver. In a low-power mode, the receiver enables a hardware over-current circuit that generates an OC INT signal when the output current exceeds a current limit.

Abstract: A semiconductor device containing a CPU capable of receiving an interrupt request signal and a task control circuit is provided. The semiconductor device includes a CPU (processor), a save circuit, and a task control circuit. The CPU includes a program counter that is updated when a task is executed. The semiconductor device includes an interrupt-related data save circuit that stores the data of the program counter when the CPU receives a CPU interrupt request signal. The data of the program counter stored in the interrupt-related data save circuit is stored in an save circuit and is used for restoring from the interrupt processing.

Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.

Abstract: A semiconductor device capable of reducing electric power consumption while suppressing deterioration in reliability is provided. The semiconductor device includes a flash memory, a SRAM formed on a SOI substrate, oscillation circuits generating a signal of a first frequency and a signal of a second frequency lower than the first frequency, and a processor operating in synchronization with a system clock. The processor performs steps of turning on a power supply of the flash memory, lowering a threshold voltage of the SRAM, transferring a program from the flash memory to the SRAM by using the signal of the first frequency as the system clock, turning off the power supply of the flash memory, heightening the threshold voltage of the SRAM, and executing the program stored in the SRAM by using the signal of the second frequency as the system clock.

Abstract: An apparatus includes a device comprising a semiconductor junction configured to generate a reference voltage, a voltage divider circuit, a comparator circuit, and a first output circuit. The voltage divider circuit may be configured to generate a first predetermined threshold voltage in response to the reference voltage. The comparator circuit may be configured to generate a first intermediate signal in response to a comparison of the first predetermined threshold voltage and an input signal. The first output circuit may be configured to generate a first output signal in response to the first intermediate signal.

Abstract: An apparatus, a method and a non-transitory computer-readable storage medium storing a program for controlling power receiving operation. The apparatus includes a controller configured to compare a frequency of an electric current generated by a voltage induced in a power receiving circuit by a magnetic field generated by a power transmitting apparatus, against a frequency threshold to determine whether the frequency is equal to or below the frequency threshold, and in response to determining that the frequency is equal to or below the frequency threshold, control a communications circuit to communicate a control command message instructing the power transmitting apparatus to modify a power charge signal used to provide the magnetic field in a manner for protecting the apparatus.

Abstract: Systems and methods for balancing a pair of battery cells are described. A controller can determine a voltage difference based on a first voltage of a first battery cell and a second voltage of a second battery cell. The controller can determine a current difference between current of an inductor and a current limit of the inductor, where the inductor can be connected to a node between the first and second battery cells. The controller can identify at least one switching elements among a plurality of switching elements based on the voltage difference and the current difference. The controller can activate the identified switching elements to perform battery cell balancing between the first battery cell and the second battery cell.

Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

Abstract: The semiconductor device includes a first electrode, a second electrode electrically coupled to the first electrode, and a third electrodes electrically coupled to at least one of the first and the second electrode, a first plating deposition portion on the first electrode, a second and a third plating deposition portions formed on the second and the third electrode, respectively. The areas of the second and the third plating deposition portion are smaller than the area of the first plating deposition portion. The periphery length of the third plating deposition portion is longer than the periphery length of the second plating deposition portion.

Abstract: A semiconductor device selects one start sequence of the normal start and the low-power-consumption start based on the determination result of the determination circuit. According to the configuration, the operation in the start sequence from the power supply input to the processor operation start can be selected from the operation in which the instantaneous current is suppressed and the high-speed operation based on the supplied power supply.

Abstract: The present embodiments are directed to methods and apparatuses for operating a battery charger in computing systems having certain system load requirements, battery configurations and external device power supply support. According to some aspects, the present embodiments provide methods and apparatuses for providing a reverse boost mode of operation when the battery charger is providing system power from a battery, such as when an adapter is not connected. The reverse boost mode of operation according to embodiments provides a regulated output voltage, thereby allowing a load such as a CPU to operate at maximum performance, even when the battery has discharged below a threshold discharge level.

Abstract: The present invention provides a current detection circuit, semiconductor device, and a semiconductor system suitable for improving a current sensing accuracy. According to one embodiment, the current detection circuit 12 comprises a sense transistor Tr11 through which a first sense current proportional to the current flowing through the drive transistor MN1 flows, an operational amplifier AMP1 for amplifying the potential difference of the voltage of the external output terminal OUT and the source voltage of the sense transistor Tr11 for outputting the first sense current, a transistor Tr12 provided in series with the sense transistor Tr11 and to which the output voltage of the operational amplifier AMP1 is applied to the gate, and a switch SW3 provided between the external output terminal OUT and the source of the sense transistor Tr11 and turned on when the drive transistor MN1 is turned off.

Abstract: A semiconductor device comprises a pulse signal output circuit providing a pulse signal for a transmission electrode of an electrode pair, a current converter converting a first current generated on the reception electrode to a second current, a current-controlled oscillator outputting an oscillation signal having a frequency depending on the second current, and a counter counting a number of oscillating times of the oscillation signal per a predetermined period; wherein the current converter comprises a first constant current source and output a combined current of the first constant current of the first constant current source and the first current as the second current in response to the pulse signal, so that the semiconductor device suppresses an increase circuit size.

Abstract: Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

Abstract: A method and a system may inductively determine a position of a display screen of a computing device. Associated processes may generate a magnetic field by providing an alternating current to a driver coil, and may generate a voltage at a sensor coil in response to the magnetic field. The system and method may additionally include determining a position of the display screen by executing an algorithm at a processor. An input to the algorithm may include voltage data associated with the voltage generated at the sensor coil.

Abstract: A current sensing circuit and a minimum operating frequency for a wireless power transmission system is presented. A method of measuring current through a wireless power transmit coil, includes receiving a signal from a switching circuit into a sampling circuit; filtering the sampled signal from the sampling circuit; biasing the filtered sampled signal, wherein the biasing occurs only when the sampling circuit is active; and amplifying the biased signal to provide a transmit coil current signal. A method of measuring current through a wireless power transmit coil, includes receiving a signal from a switching circuit into a sampling circuit; filtering the sampled signal from the sampling circuit; biasing the filtered sampled signal, wherein the biasing occurs only when the sampling circuit is active; and amplifying the biased signal to provide a transmit coil current signal.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.

Abstract: A radio communication device includes an application execution unit which generates first transmission data including first application identification information, a communication unit which receives a message including first reception data including the first application identification information, and an occupancy rate determination unit including a transmission ID number counter which counts the number of first application identification information included in the first transmission data and which outputs a count result as a first transmission ID count value, a reception ID number counter which counts the number of first application identification information included in the first reception data and which outputs a count result as a first reception ID count value, and a comparison unit which compares the first transmission ID count value with the first reception ID count value to determine the number of transmission data and the number of reception data have a predetermined ratio.