Patents Assigned to RENESAS
  • Semiconductor device and method of manufacturing semiconductor device
    Patent number: 11329152
    Abstract: A method of manufacturing a semiconductor device of one embodiment includes the steps of: forming a drift region in a first surface of a semiconductor substrate; forming a body region having a first portion disposed in the first surface, and a second portion disposed in the first surface so as to surround the first portion and the drift region; forming a hard mask, having an opening over the drift region, in the first surface; forming a reverse conductivity region in the first surface by ion implantation using the hard mask; forming a trench in the first surface by anisotropic etching using the hard mask; and embedding an isolation film in the trench. The ion implantation is performed obliquely to the first surface such that ions are implanted below a first edge part, which is located on a first portion side of the opening, of the hard mask.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: May 10, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki Sekikawa, Takahiro Mori, Yuji Ishii
  • Semiconductor device
    Patent number: 11322668
    Abstract: A semiconductor device includes a substrate, an optical element, and a semiconductor element. The substrate includes a first region and a second region which are regions differing from each other. The optical element is formed in one of the first region and the second region. The electric element is formed in another of the first region and the second region. The first region includes a first insulating layer and a first semiconductor layer formed on the first insulating layer. The second region includes the first insulating layer, the first semiconductor layer, a second insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 3, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seigo Namioka, Yasutaka Nakashiba
  • POSITION SENSOR SYSTEM
    Publication number: 20220128381
    Abstract: A position sensor system having at least two receiver coil sets, at least one transmitter coil and a signal conditioning and processing unit, wherein each receiver coil set of the at least two receiver coil sets includes at least two separate receiver coils including a sine receiver coil and a cosine receiver coil, wherein the signal conditioning and processing unit is contained in an integrated circuit, and wherein the at least two receiver coil sets, the at least one transmitter coil and the integrated circuit containing the signal conditioning and processing unit are located on a printed circuit board.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 28, 2022
    Applicant: Renesas Electronics America Inc.
    Inventors: Rudolf PICHLER, Josef JANISCH, Thomas OSWALD
  • Open condition sensing and protection
    Patent number: 11316502
    Abstract: Systems and methods for detecting an open condition in a master-slave configuration are described. In an example, a controller can be integrated in a slave device of a master-slave configuration. The controller can be configured to activate a current source to supply a current to a pin of the slave device. The controller can be further configured to compare a voltage measured at the pin of the slave device with a reference voltage. The controller can be further configured to, based on the comparison, determine a presence or an absence of an open condition associated with the pin of the slave device. The controller can be further configured to output a signal representing the determination of the presence or the absence of the open condition to a master device.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 26, 2022
    Assignee: Renesas Electronics America Inc.
    Inventors: Chun Cheung, Keerthi Varman Anna Jayaprakash, Fumihito Hayashi, Yuji Ikeda
  • DATA PROCESSING DEVICE
    Publication number: 20220121442
    Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Sugako OHTANI, Hiroyuki KONDO
  • Data driven embedded application building and configuration
    Patent number: 11307833
    Abstract: Provided herein are various systems, methods and architectures for enabling a microcontroller manufacturer to provide certain modification and configuration functionality to product vendors, while still maintaining the level of control needed to ensure that a product vendor does not inadvertently (or otherwise) create code that causes the microcontroller to not work properly. In one embodiment, this functionality can be performed through the steps of displaying a set of microcontroller properties that are available for configuration, receiving user information regarding a first value corresponding to a first microcontroller property, determining whether the user information results in a valid microcontroller configuration, and in response to determining that the user information results in a valid microcontroller configuration, generating compiled code for the microcontroller.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 19, 2022
    Assignee: RENESAS ELECTRONICS AMERICA INC.
    Inventors: Jon Matthew Brabender, John L. Dallaway, Mark Goodchild, James Mark Deadman, Brandon Cranford Hussey, Kristine M. Jassmann
  • Semiconductor device
    Patent number: 11307479
    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba
  • Semiconductor device
    Patent number: 11309705
    Abstract: A semiconductor device includes a bridge circuit comprising first to fourth elements, a first diagnostic circuit that detects a potential difference between two intermediate nodes of the bridge circuit and a control circuit that detects a failure of the first or second element based on an output of the first diagnostic circuit, wherein the first and second elements are first and second power transistors connected in series.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akio Kamimoto
  • Semiconductor device including a fin-type transistor and method of manufacturing the same
    Patent number: 11302791
    Abstract: In order to improve the reliability of a semiconductor device, in a memory cell of a split-gate type MONOS memory formed on a fin, a drain region is formed in an epitaxial layer on the fin, and a source region is formed in the fin, and a silicide layer is formed on an upper surface of the fin in which the source region is formed.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Semiconductor device
    Patent number: 11302596
    Abstract: A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: April 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Hironobu Miyamoto, Masami Sawada
  • Electric power transmitting device, non-contact power supply system, and control method
    Patent number: 11303325
    Abstract: A non-contact power supply system is provided employing an electric power transmitting device which can improve the transmission efficiency of electric power, suppressing the circuit scale. The electric power transmitting device is configured with a resonance circuit including a resonance capacity and a resonance coil acting as a transmitting antenna, and a first coil arranged magnetically coupled with the resonance coil. The electric power transmitting device transmits electric power in a non-contact manner using resonant coupling of the resonance circuit. When transmitting the electric power, the electric power transmitting device controls the first coil to connect or disconnect both ends thereof so as to bring a resonance frequency of the resonance circuit close to a frequency of an electric power transmission signal outputted as the electric power to be transmitted.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Katsuei Ichikawa
  • Semiconductor device
    Patent number: 11302828
    Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Digh Hisamoto, Yoshiyuki Kawashima, Takashi Hashimoto
  • Semiconductor device
    Patent number: 11296118
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Uejima, Kazuhiro Koudate
  • Semiconductor device and method of manufacturing the same
    Patent number: 11296219
    Abstract: In a deep trench DTC reaching a predetermined depth from a first main surface of a semiconductor substrate SUB, a plurality of columnar conductors CCB including plugs PUG and field plates FP are formed. A p type impurity layer PIL is formed along the side wall surface of the deep trench DTC. Between the bottom of the plug PUG and the bottom of the p type impurity layer PIL, the field plate FP and the p type impurity layer PIL are positioned to face each other via an insulating film FIF interposed therebetween. Between the bottom of the p type impurity layer PIL and the bottom of the field plate FP, the field plate FP and an n-type drift layer NDL of the semiconductor substrate SUB are positioned to face each other via the insulating film FIF interposed therebetween.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Semiconductor device including a bus arbiter
    Patent number: 11294835
    Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Support apparatus and design support method
    Patent number: 11294647
    Abstract: A storage device stores a source code and a model created by referencing a source code. A processor generates a terminal generation setting file in which a terminal of a code block is written, by searching a terminal block included in the model read from the storage device and defining the terminal of the code block based on the terminal block obtained from a search result of the terminal block. Further, the processor writes, in the code block, a terminal linking code indicating a correspondence relationship between the terminal written in the terminal generation setting file and the source code. Furthermore, the processor compiles, using the terminal generation setting file, the code block in which the terminal linking code is written into a format executable in the model execution environment.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuji Tsuda, Saika Arai
  • Power amplifier biasing network providing gain expansion
    Patent number: 11296655
    Abstract: An apparatus includes an amplifier and a bias network. The amplifier generally has a predefined linear range. The bias network is generally connected to an input of the amplifier. The bias network generally comprises a linearizer configured to provide gain expansion and extend linearity of the amplifier beyond the predefined linear range.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 5, 2022
    Assignee: Renesas Electronics America Inc.
    Inventors: Hojung Ju, Roberto Aparicio Joo, John Zhao, Jason May
  • Method for increasing the position measurement accuracy using inductive position sensor
    Patent number: 11293744
    Abstract: An accurate position sensor that operates over a long range is provided. The position sensor can include a first sensor coil having a first number of periods over a range of motion of a target; and a second sensor coil having a second number of periods over the range, wherein the first number of periods is different from the second number of periods, and wherein the first sensor coil and the second sensor coil are arranged with respect to one another such that the target engages both of them simultaneously. In some embodiments, the first number of periods is one and the second number of periods is greater than one. In some embodiments, the first number of periods is greater than one and the second number of periods is greater than the first number of periods.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: April 5, 2022
    Assignee: Renesas Electronics America Inc.
    Inventors: Giovanni Bertini, Monica Mathisen, Ivo Binda, Ruggero Leoncavallo
  • SECURE ENCRYPTION KEY GENERATION AND MANAGEMENT IN OPEN AND SECURE PROCESSOR ENVIRONMENTS
    Publication number: 20220103354
    Abstract: Example implementations include a method of generating a first authentication code based at least partially on an authentication key and an application key, transmitting to a secure subsystem of the local processing device the authentication key, the application key, and the first authentication code, generating, at the secure subsystem, a second authentication code based at least partially on the authentication key and the application key, and generating, at the secure subsystem, a secure application key, in accordance with a determination that the first authentication code and the second authentication code satisfy an authentication criterion.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Renesas Electronics Corporation
    Inventor: Giancarlo PARODI
  • METHOD AND SYSTEM FOR GENERATING AND ACCESSING GUARD SERVICES FOR SECURE SERVICES AND OPERATIONS THEREOF
    Publication number: 20220100844
    Abstract: Example implementations include generating a guard service for a secure service at a secure region of a processing system by detecting a call to a secure service at a secure region of a processing device, obtaining a secure interface associated with the secure service, generating a guard interface based at least partially on the secure interface, generating a guard service based at least partially on the guard interface, locating the guard service at a secure region, and locating the guard interface at a secure address at the secure region.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Applicant: Renesas Electronics Corporation
    Inventors: Kimberly DINSMORE, Brandon HUSSEY