Abstract: A device includes an interface and Time Division Multiple Access (TDMA) Medium Access Control (MAC) circuitry coupled to the interface. The TDMA MAC circuitry detects a beacon in a frame having a defined frame duration and determines a frame compensation value based on a start time of the frame, a reference start time of the frame, and a number of elapsed frames. A current frame duration value is determined based on the frame compensation value and the defined frame duration.

Abstract: An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Abstract: In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.

Abstract: A device for detecting the concentration of biological materials is formed in a body having a plurality of fluidic paths connectable to a multi-microbalance structure carrying a plurality of microbalances, each microbalance having a sensitive portion facing a reaction chamber. The body and the multi-microbalance structure are configured to be mechanically coupled together and each microbalance is configured to be coupled to a respective fluidic path. Each fluidic path includes an inlet, a duct and a liquid waste, each duct being configured to be coupled with a respective reaction chamber. The plurality of fluidic paths and microbalances form at least one first and one second reference cells and one first sample cell.

Abstract: A sensing element integrated in a semiconductor material chip has a sensing diode of a junction type configured to be reverse biased so that its junction capacitance is sensitive to the local temperature. A reading stage is coupled to the sensing element for detecting variations of the junction capacitance of the sensing diode and outputting a reading acquisition signal proportional to the local temperature of the sensing diode. The sensing diode has a cathode terminal coupled to a biasing node and an anode terminal coupled to a first input of the reading stage. The biasing node receives a voltage positive with respect to the first input of the reading stage for keeping the sensing diode reverse biased.

Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

Abstract: An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.

Abstract: A quartz crystal resonator is connected to an array of switchable capacitors or resistors. The switched actuation of elements of the array is controlled by bits of a control word. At least one of the bits of the control word is controlled by pulse width modulation to effectuate a tuning of the oscillation frequency of the quartz crystal resonator.

Abstract: A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

Abstract: A quartz crystal resonator is coupled to an electronic circuit. A capacitive or resistive element is provided for adjusting a frequency of the quartz crystal resonator on activation or deactivation of a function of a circuit. Control is made according to a model of an expected variation of a temperature of the quartz crystal resonator.

Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

Abstract: A projector includes a first laser source projecting a first laser beam, a second laser source projecting a second laser beam at an angle with respect to the first laser beam, and a mirror reflecting the first and second laser beams. Circuitry controls the mirror to simultaneously reflect the first and second laser beams in a first scan pattern to form a first image having a number of scan lines greater than two times a horizontal resonance frequency of the mirror divided by a desired frame rate of the first image. The first laser beam forms a first angle of incidence with the mirror and the second laser beam forms a second angle of incidence with the mirror, the second angle of incidence being equal to the first angle of incidence summed with the angle of the second laser beam with respect to the first laser beam.

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

Abstract: An inkjet print head includes a semiconductor substrate having a plurality of continuous slotted recesses in a first surface. The plurality of continuous slotted recesses is arranged in parallel, spaced apart relation. Each continuous slotted recess extends continuously across the first surface. The semiconductor substrate also has a plurality of discontinuous slotted recesses in a second surface that is opposite the first surface. The plurality of discontinuous slotted recesses is aligned and coupled in communication with the continuous slotted recesses to have a first portion defining a plurality of alternating through-wafer channels and a second portion defining residual slotted recess portions. A dielectric material is disposed within the residual slotted recess portions. A plurality of inkjet heaters is carried by said semiconductor substrate.

Abstract: A rectifier cell includes a first cell branch and a second cell branch that extend in parallel between two opposite nodes receiving an a.c. signal. The first cell branch includes a first pair of transistors arranged with their current paths cascaded, with a first intermediate point in-between. The second cell branch includes a second pair of transistors arranged with their current paths cascaded, with a second intermediate point in-between. Each of the pairs of transistors includes a first transistor with a control terminal coupled to one of the two opposite nodes and a second transistor with a control terminal coupled to the other of the two opposite nodes. The bulks of the transistors receive voltages in order to vary the transistor threshold voltage by bringing the threshold voltage to a first value during forward conduction and to a second value during reverse conduction.

Abstract: Systems and methods for switching on and off a power amplifier including a signal input receiving an input signal and a signal output providing an output signal. The power amplifier includes a control input receiving a gain control signal indicating a requested gain and a control input receiving a mute control signal indicating whether the signal output should be switched on or switched off. A control unit determines whether the signal output of the power amplifier should be switched on and/or off, and if switched on receives data identifying a switch-on ramp and if switched off receives data identifying a switch-off ramp. The control unit generates the mute control signal to switch on the signal output of the power amplifier on or off, and generates the gain control signal as a function of the data identifying the switch-on or switch-off ramp to thereby increase or decrease the gain control signal.

Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Abstract: A ToF SPAD based range detecting module is configurable for operation in a first mode to make a distance determination relative to an object within a field of view. The ToF SPAD based range detecting module is further configurable for operation in a second mode to engage in bi-directional data communication with another apparatus within the field of view.

Abstract: A photosensitive diode has an anode terminal and a cathode terminal. A passive quench resistance circuit includes a resistor with a variable resistance that is controlled by a control signal. The resistor is electrically connected to the cathode terminal. The resistor of the passive quench resistance circuit is formed by a first semiconductor region. The control signal is applied to a control gate of the passive quench resistance circuit. The control gate is formed by a second semiconductor region that is insulated from the first semiconductor region and extends parallel to the first semiconductor region. The voltage of the control signal applied to the control gate controls the variable resistance.