Abstract: A power conversion device includes an enclosure containing one or more drops of a liquid. A capacitive electret transducer is coupled to the enclosure. In response to applied heat at a heating surface, the liquid vaporizes and then condenses on a flexible membrane of the capacitive electret transducer. The flexible membrane is displaced in response to the vaporization-condensation and the capacitive electret transducer generates an output current.

Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.

Abstract: A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die.

Abstract: Methods are directed to forming an electronic semiconductor device that includes a body having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side. A body region extends in the second structural region at the first side. A source region extends inside the body region and a lightly-doped drain region faces the first side of the body. A gate electrode is formed over the body region. A trench dielectric region extends through the second structural region in a first trench conductive region immediately adjacent to the trench dielectric region. A second trench conductive region is in electrical contact with the body region and source region. An electrical contact on the body is in electrical contact with the drain region through the first structural region.

Abstract: A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.

Abstract: An RFID transponder device has antenna terminals for coupling an antenna system to the device. A transmitter and a receiver are coupled to the antenna terminals. The device has at least one damping resistance connected to at least one of the antenna terminals. The at least one damping resistance is connected, depending on a voltage swing at the antenna terminals during a transmission burst period, either together with a serially connected switch in parallel to the antenna terminals that are coupled to the receiver, or together with a parallel connected switch between one of the antenna terminals and a terminal of the transmitter. A damping control is configured to activate the at least one damping resistance during a damping period after the transmission burst period by controlling the respective switch.

Abstract: A rectifying circuit including: between a first terminal of application of an AC voltage and a first rectified voltage delivery terminal, at least one first diode; and between a second terminal of application of the AC voltage and a second rectified voltage delivery terminal, at least one first anode-gate thyristor, the anode of the first thyristor being connected to the second rectified voltage delivery terminal; and at least one first stage for controlling the first thyristor, including: a first transistor coupling the thyristor gate to a terminal of delivery of a potential which is negative with respect to the potential of the second rectified voltage delivery terminal; and a second transistor connecting a control terminal of the first transistor to a terminal for delivering a potential which is positive with respect to the potential of the second rectified voltage delivery terminal, the anode of the first thyristor being connected to the common potential of voltages defined by said positive and negative p

Abstract: A control unit for a switching converter has an inductor element coupled to an input and a switch element coupled to the inductor element. The control unit generates a command signal with a switching period to control the switching of the switch element and to determine a first time period where an inductor current is flowing in the inductor element for storing energy and a second time period where energy is transferred to a load. The second time period has an end portion where the inductor current drops to zero. The control unit determines the duration of the first time period based on a comparison between a sensing voltage, indicative of the peak value of the inductor current, and a reference voltage. A pre-distortion stage pre-distorts the reference voltage in order to compensate for a corresponding distortion on an input current of the converter compared to a desired sinusoidal characteristic.

Abstract: A circuit has a first window comparator determining whether a signal at a first input has a voltage higher than a first threshold but lower than a second threshold, and a second window comparator determining whether a signal at a second input has a voltage higher than the first threshold but lower than the second threshold. A logic circuit generates pulses in response to either the first window comparator determining that the signal at the first differential input has a voltage higher than the first threshold but lower than the second threshold or the second window comparator determining that the signal at the second input has a voltage higher than the first threshold but lower than the second threshold. A filter circuit receives the pulses from the logic circuit and generates a flag indicating that the signal is invalid, based upon pulses received from the logic circuit.

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Abstract: A system in package encloses a sensor and motor driver circuit. In an implementation, the sensor is an integrated circuit micro-electro-mechanical-systems (MEMS) sensor and the driver circuit is a motor driver circuit. Non-motor winding data information is sensed by the MEMS sensor and processed for the purpose of characterizing known fault patterns for motors; characterizing normal operation of the motor; and evaluating continued operation of the motor to detect abnormal motor behavior and instances of motor fault. The motor is driven using PWM control and the information output by the MEMS sensor is sampled at sampling times having a fixed timing relationship relative to the PWM control signals.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: Disclosed herein is a laser projection system including a laser projector emitting a laser beam, a movable mirror apparatus reflecting the laser beam toward a surface, and a graphics processing unit (GPU). The GPU is configured to receive video data, estimate a varying speed of movement of the movable mirror apparatus for different positions of the laser beam across the surface, and process the video data based upon the estimated varying speed of movement. An application specific integrated circuit (ASIC) receives the processed video data, and to generate a beam position control signal based upon required or desired movement of the movable mirror apparatus. A laser driver controls the laser projector as a function of the processed video data, and a mirror controller controls the movable mirror apparatus as a function of the beam position control signal.

Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material.

Abstract: An electric transformer device (balun) is formed on a support plate having a first base face and an opposite second base face. The balun includes a first port (40) connectable to an electrical line for a differential signal and a second port connectable to an electrical line for a single-ended signal. A first printed conductive track is associated to the first base face of the support plate for connecting the first port to the second port. A printed conductive path is associated to the second base face of the support plate for connecting the first port to the second port. The printed conductive path is formed of a symmetric second and third printed conductive tracks.

Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region the includes a bulge region.

Abstract: A battery encapsulation method includes disposing an active battery layer on each of a plurality of battery substrates, with each battery substrate having a greater area than its corresponding active battery layer. The plurality of battery substrates are attached to an interposer having a greater area than an aggregate area of the plurality of battery substrates. The active battery layers are environmentally sealed by disposing a film over the active battery layers sized such that the film extends beyond the active battery layers to contact the battery substrates and the interposer. The interposer is physically along locations where the film contacts the interposer so as to form a plurality of battery units, with each battery unit including one of the battery substrates with the associated active battery layer disposed thereon and being environmentally sealed by the film.

Abstract: A voltage regulator having bias current boosting is provided. The voltage regulator includes a power stage for providing an output voltage to a load. The voltage regulator includes a differential stage that receives a feedback voltage representative of the output voltage and a reference voltage and controls the power stage based on a difference between the reference voltage and the feedback voltage. The voltage regulator includes a bias current boosting stage that receives the feedback and reference voltages. The bias current boosting stage provides a boosted bias current having a current level that is based on the difference between the reference and feedback voltages. The boosted bias current biases the differential stage and hastens a response of the differential stage, in response to a change in the difference between the reference voltage and the feedback voltage, in controlling the power stage.