Abstract: A mirror micromechanical structure has a mobile mass carrying a mirror element. The mass is drivable in rotation for reflecting an incident light beam with a desired angular range. The mobile mass is suspended above a cavity obtained in a supporting body. The cavity is shaped so that the supporting body does not hinder the reflected light beam within the desired angular range. In particular, the cavity extends as far as a first side edge wall of the supporting body of the mirror micromechanical structure. The cavity is open towards, and in communication with, the outside of the mirror micromechanical structure at the first side edge wall.

Abstract: An AMR-type integrated magnetoresistive sensor sensitive to perpendicular magnetic fields is formed on a body of semiconductor material covered by an insulating region. The insulating region houses a set/reset coil and a magnetoresistor arranged on the set/reset coil. The magnetoresistor is formed by a magnetoresistive strip of an elongated shape parallel to the preferential magnetization direction. A concentrator of ferromagnetic material is arranged on top of the insulating region as the last element of the sensor and is formed by a plurality of distinct ferromagnetic regions aligned parallel to the preferential magnetization direction.

Abstract: A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.

Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.

Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.

Abstract: An encapsulation cover for an electronic package includes a cover body having a frontal wall provided with at least one optical element allowing light to pass through. The optical element is inserted into the encapsulation cover by overmolding into a through-passage of the frontal wall. A front face of the optical element is set back with respect to a front face of the frontal wall. The process for fabricating the encapsulation cover includes forming a stack of a sacrificial spacer on top of an optical element, with the stack placed into a cavity of a mold.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.

Abstract: A driving apparatus configured to drive a light emitting device includes a driving current source module operable to supply current to the light emitting device via a node during operation. A protection module coupled to the node and the driving current source module selectively injects current to the node during operation. The driving current source module is controlled based on a detection result of a voltage on the node.

Abstract: A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

Abstract: A method and near field communications (NFC) system for sensing at least one of an environmental condition or a composition of media in a proximity of the NFC system are provided. In the method and system, a first antenna irradiates an electromagnetic field during a sensor mode. A second antenna detects the electromagnetic field and outputs a voltage representative of the detected electromagnetic field. An NFC controller receives a signal representative of the voltage. The NFC controller determines at least one of the environmental condition or the composition of media based on an association stored in memory between the voltage and the at least one of the environmental condition or the composition of media.

Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

Abstract: A directional loudspeaker system has a loudspeaker arrangement configured to generate N audio signals. A time-of-flight sensor arrangement is configured to detect a location of a user. A controller is configured to use information from the time-of-flight sensor arrangement about the location of the user to control the delay such that the N audio signals constructively interfere at the location of the user.

Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.

Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.