Patents Assigned to STMicroelectronics AS
  • Patent number: 10303201
    Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Pirozzi
  • Patent number: 10303234
    Abstract: An integrated processing unit is supplied by a power supply voltage present at the terminals of a capacitor configured to supply a maximum permissible voltage drop. A periodic pulse signal is generated having a period that is less than or equal to a current period determined from the maximum permissible voltage drop and a current consumption of the processing unit. The power supply voltage is compared with a threshold voltage at the pulse rate of the periodic pulse signal. A control signal generated from that comparison is delivered to the processing unit and has a first value when the power supply voltage is greater than or equal to the threshold voltage and a second value when the power supply voltage is less than the threshold voltage.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Bruno Gailhard
  • Patent number: 10302693
    Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 28, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Chittoor Parthasarathy
  • Patent number: 10303299
    Abstract: Disclosed herein is a touch screen controller operable with a touch screen. The touch screen controller includes input circuitry configured to receive touch data from the touch screen, and processing circuitry. The processing circuitry is configured to identify an island in the touch data, determine whether a horizontal groove is present in the island, determine whether a vertical groove is present in the island, and determine whether a diagonal groove is present in the island. The processing circuitry determines the island to indicate a single elongated touch where a diagonal groove is present in the island but horizontal and vertical grooves are not present in the island.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Manivannan Ponnarasu, Mythreyi Nagarajan
  • Patent number: 10302700
    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Vinay Kumar, Pramod Kumar
  • Patent number: 10306248
    Abstract: A method and device for real-time generation of a multiresolution representation of a digital image for real-time generation are disclosed. A sequence of main representations of the digital image is stored at successive different main resolutions in a main memory. A part of a current main representation is loaded from the main memory into a local memory via a bus. A current main representation is processed by determining a corresponding part of an intermediate representation of the image having an intermediate resolution lying between the resolution of the current main representation and the resolution of the subsequent main representation. The loading and processing steps are repeated for other parts of the current main representation until all parts of the current main representation have been successively loaded and processed.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 28, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Jacques Talayssat, Sébastien Cleyet-Merle, Vitor Schwambach Costa
  • Patent number: 10304893
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Patent number: 10303193
    Abstract: A dual-input, single-output low-dropout voltage regulator circuit includes: a first supply terminal, a second supply terminal and an output terminal, and first and second transistors having current paths coupled respectively between the first and second terminal and the output terminal. First and second drive circuit blocks are coupled respectively to the first and second supply terminals and drive the control terminals of the first and second transistors to provide a regulated voltage at the output terminal from the voltage on the first supply terminal and the second supply terminal. An input circuit block is sensitive to the voltage at the output terminal and is coupled to the first and second drive circuit blocks and configured to activate the second transistor to provide regulated voltage at the output terminal from the second terminal as a result of the voltage at the output terminal becoming lower than a desired value.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Sautto, Davide Betta, Agostino Mirabelli
  • Publication number: 20190157469
    Abstract: An encapsulation cover for an electronic package includes a frontal wall with a through-passage extending between faces. The frontal wall includes an optical element that allows light to pass through the through-passage. A cover body and a metal insert that is embedded in the cover body, with the cover body being overmolded over the metal insert, defines at least part of the frontal wall.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 23, 2019
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine SAXOD, Veronique FERRE, Agnes BAFFERT, Jean-Michel RIVIERE
  • Publication number: 20190158069
    Abstract: An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Applicant: STMicroelectronics SA
    Inventors: Bruno GRELAUD, Sebastien PRUVOST
  • Publication number: 20190155018
    Abstract: A method for controlling operation of a MEMS mirror includes steps for: generating activation pulses for operating the MEMS mirror and generating a window activation signal for current detection, with the window activation signal overlapping with an end of an activation pulse. The method also includes detecting current through a stator or a rotor of the MEMS mirror during the window activation signal and terminating a current activation pulse and the window activation signal in response to detecting a change in the direction of the current through the stator or the rotor of the MEMS mirror during the window activation signal.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: STMicroelectronics Ltd
    Inventor: Sason SOURANI
  • Publication number: 20190158070
    Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Mohit Singh, Ankur Bal
  • Patent number: 10295416
    Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Nitin Bansal
  • Patent number: 10298119
    Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Phalguni Bala, Hiten Advani
  • Patent number: 10296441
    Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTD
    Inventors: Xiao Kang Jiao, PengFei Zhu
  • Patent number: 10298295
    Abstract: A method can be used for detecting a potential presence of an object by a reader capable of mutually communicating via a contactless communications protocol. An antenna of the reader transmits a magnetic field on a carrier signal having a sub-carrier modulated by a first data sequence. The modulated sub-carrier is non-interpretable by the object. The antenna of the reader receives a signal resulting from the transmission. The reader demodulates the sub-carrier of the resulting signal so as to extract a second data sequence from the resulting signal. The first data sequence and second data sequence are correlated and the potential presence or absence of the object is determined based upon the result of the correlating.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Patent number: 10295577
    Abstract: In an embodiment, a current sense circuit includes a copy transistor having a gate configured to be coupled to a gate of an output transistor, and a drain coupled to an input terminal. The drain of the copy transistor is configured to be coupled to a drain of the output transistor. A first transistor has a current path coupled to a current path of the copy transistor. An error amplifier has a non-inverting input coupled to a source of the copy transistor, an inverting input configured to be coupled to a source of the output transistor, an output coupled to a gate of the first transistor, a positive power supply terminal coupled to the input terminal and a negative power supply terminal coupled to a reference supply terminal. A current-to-voltage converter has an input coupled to the current path of the copy transistor.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics Design & Application S.R.O.
    Inventor: Sandor Petenyi
  • Patent number: 10294096
    Abstract: In order to manufacture a packaged device, a die having a sensitive region is bonded to a support, and a packaging mass of moldable material is molded on the support so as to surround the die. During molding of the packaging mass, a chamber is formed, which faces the sensitive region and is connected to the outside environment. To this end, a sacrificial mass of material that may evaporate/sublimate is dispensed on the sensitive region; the packaging mass is molded on the sacrificial mass; a through hole is formed in the packaging mass to extend as far as the sacrificial mass; the sacrificial mass is evaporated/sublimated through the hole.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10298178
    Abstract: A communication apparatus includes an antenna and a receive chain. The receive chain includes a switching transistor, and amplification transistor and a discharge transistor. The amplification transistor has a control terminal coupled to a current path terminal of the switching transistor. The discharge transistor has a current path coupled between the control terminal of the amplification transistor and a ground terminal. The discharge circuit is configured to discharge an intrinsic capacitance of the switching circuit when the switching transistor is in an off state.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics SA
    Inventor: Laurent Chabert
  • Patent number: 10298408
    Abstract: Power and data are transmitted via a transformer including primary side and secondary side. A primary side signal is generated by coupling a first oscillator signal modulated with a data signal with a second oscillator signal that is selectively switched on and off. At the secondary side a secondary signal is generated. A demodulator demodulates the secondary signal to recover the data signal. A rectifier processes the secondary signal to recover a power supply signal controlled by switching on and off the second oscillator.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Egidio Ragonese, Nunzio Greco, Giuseppe Palmisano