Abstract: A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.

Abstract: A control circuit controls a switch of a switching current converter receiving an input quantity, with a transformer having a primary winding and a sensor element generating a sensing signal correlated to a current in the primary winding. The control circuit has a comparator stage configured to compare a reference signal with a comparison signal correlated to the sensing signal and generate an opening signal for the switch. The comparator stage has a comparator element and a delay-compensation circuit. The delay-compensation circuit is configured to generate a compensation signal correlated to the input quantity and to a propagation delay with respect to the opening signal. The comparator element generates the opening signal with an advanced timing correlated to the input quantity and to the propagation delay.

Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.

Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.

Abstract: An avalanche diode includes a PN junction with a first deep trench structure adjacent to the PN junction. An area via which photons impinge is provided, the PN junction extending substantially vertically with respect to the area. An avalanche diode array can be formed to include a number of avalanche diodes.

Abstract: A magnetic energy harvesting and scavenging circuit includes a first substrate having a first surface and a second surface. An energy harvesting and scavenging coil is formed proximate the first surface. An electromechanical systems device, which may be a MEMS device, includes a moveable mass that extends over the first surface of the first substrate and may be displaced relative to the substrate in three dimensions responsive to an external force applied to the moveable mass. The movable mass includes at least one permanent magnet that is magnetically coupled to the energy harvesting and scavenging coil. Energy harvesting and scavenging circuitry, which may be formed in the first substrate where the first substrate is a semiconductor chip, is electrically coupled to the energy harvesting and scavenging coil and generates electrical energy due to magnetic flux variation through the energy harvesting and scavenging coil responsive to movement of the moveable mass.

Abstract: An AC/DC converter includes a first terminal and a second terminal to receive an AC voltage and a third terminal and a fourth terminal to deliver a DC voltage. A rectifying bridge is provided in the converter. A controllable switching or rectifying element has a control terminal configured to receive a control current. A first switch is coupled between a supply voltage and the control terminal to inject the control current. A second switch is coupled between the control terminal and a reference voltage to extract the control current. The first and second switches are selectively actuated by a control circuit.

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract: A Geostationary Earth Orbit (GEO) satellite belonging to a constellation of satellites of a BeiDou navigation system is acquired at a GNSS receiver. Conducting the acquisition includes finding the edge of a data bit in a signal carrying a data stream of a given satellite in order to start a locked tracking phase and demodulating the data stream of the GEO satellite. Detecting the edge of the data bit includes performing, at the GNSS receiver, a coherent power accumulation over a constant data cycle, starting from two respective possible initial positions in the sequence of data. Detecting the edge of the data bit also includes computing a tracking ratio parameter as the ratio of the two coherent power accumulations multiplied by a constant value.

Abstract: A memory cell includes a phase-change material. A via is electrically connected with a transistor and an element for heating the phase-change material. An electrically-conductive thermal barrier is positioned between the via and the heating element.

Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10?5 ?·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.

Abstract: An encapsulation cover for an electronic package is formed by a first cover body and a second cover body. The first and second cover bodies are assembled together by a bonding material. Frontal walls of the first and second cover bodies are superposed and include through-passages that facing one another and are provided with optical elements allowing light to pass through. At least one surface of the frontal walls of the first and second cover bodies includes void containing the bonding material.

Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

Abstract: An electronic device includes a time-of-flight sensor configured to sense a distance between the electronic device and at least one object proximate the electronic device. Processing circuitry is coupled to the time-of-flight sensor and controls access to the electronic device based on the sensed distance. The electronic device may include a digital camera that the processing circuitry controls to perform facial or iris recognition utilizing the sensed distance from the time-of-flight sensor.

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

Abstract: Disclosed herein is a device including a MEMS sensor configured to generate a first differential capacitance representing a change in capacitance from a first original sensing capacitance value and a second differential capacitance representing a change in capacitance from a second original sensing capacitance value, with the first and second original sensing capacitance values being mismatched. A compensation circuit is configured to generate outputs for compensating the first and second differential capacitances for the mismatch. A capacitance to voltage converter receives the first and second differential capacitances and the outputs of the compensation circuit as input and generates an output voltage as a function thereof.

Abstract: A MEMS sensor device provided with a sensing structure, having: a substrate with a top surface extending in a horizontal plane; an inertial mass, suspended over the substrate; elastic coupling elements, elastically connected to the inertial mass so as to enable inertial movement thereof with respect to the substrate as a function of a quantity to be detected along a sensing axis belonging to the horizontal plane; and sensing electrodes, capacitively coupled to the inertial mass so as to form at least one sensing capacitor, a value of capacitance of which is indicative of the quantity to be detected. The sensing structure moreover has a suspension structure, to which the sensing electrodes are rigidly coupled, and to which the inertial mass is elastically coupled through the elastic coupling elements; the suspension structure is connected to an anchorage structure, fixed with respect to the substrate, by means of elastic suspension elements.

Abstract: Various embodiments provide a resonant converter that includes a synchronous rectifier driver. The synchronous rectifier driver reduces voltage spikes on drains of transistors within the resonant converter by placing an active clamp between the drains of the transistors and an output terminal of the resonant converter. The active clamp reduces the voltage spikes by sinking current at the drains of the transistors to an output capacitor. By sinking the current to the output terminal, power loss is minimized and efficiency of the resonant converter is improved.

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.