Patents Assigned to STMicroelectronics AS
  • Publication number: 20190113943
    Abstract: An electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. A method for operating the device to switch into a power on mode includes: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. A method for operating the device to switch into a power down mode includes: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Kapil Kumar TYAGI, Nitin GUPTA
  • Publication number: 20190115524
    Abstract: A MEMS piezoelectric device includes a monolithic semiconductor body having first and second main surfaces extending parallel to a horizontal plane formed by first and second horizontal axes. A housing cavity is arranged within the monolithic semiconductor body. A membrane is suspended above the housing cavity at the first main surface. A piezoelectric material layer is arranged above a first surface of the membrane with a proof mass coupled to a second surface, opposite to the first surface, along the vertical axis. An electrode arrangement is provided in contact with the piezoelectric material layer. The proof mass causes deformation of the piezoelectric material layer in response to environmental mechanical vibrations. The proof mass is coupled to the membrane by a connection element arranged, in a central position, between the membrane and the proof mass in the direction of the vertical axis.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 18, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Maria Fortuna BEVILACQUA, Flavio Francesco VILLA, Rossana SCALDAFERRI, Valeria CASUSCELLI, Andrea DI MATTEO, Dino FARALLI
  • Publication number: 20190113999
    Abstract: A method includes upon sensing a touch to a first location on a touch display, reporting first coordinates of the touch. After sensing movement of the touch along a first path from the first location to a second location more than a tolerance distance away, intermediate coordinates of the touch along the first path that are not more than a cutoff distance away are reported such that there is a first gap between a last reported intermediate coordinate and the second location. After sensing movement of the touch along a second path from the second location to a third location more, second coordinates of the touch are reported, the second reported coordinates of the touch being a point along the first path that is calculated by subtracting the first gap from a distance between the first location and the third location, and then adding a first compensation difference thereto.
    Type: Application
    Filed: November 3, 2017
    Publication date: April 18, 2019
    Applicants: STMicroelectronics (Beijing) R&D Co. Ltd, STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hank Yin, Cam Chung La, Janet Sun
  • Publication number: 20190113897
    Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 18, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • Publication number: 20190113415
    Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe GROSSE, Patrick LE MAITRE, Jean-Francois CARPENTIER
  • Patent number: 10263021
    Abstract: Disclosed herein is an electronic device including an integrated circuit substrate, with a pixel array area within the integrated circuit substrate. A first deep trench isolation structure is formed in the integrated circuit substrate about a perimeter of the pixel array area. First, second, third, and fourth pixels are within the pixel array area and spaced apart from one another. A storage capacitor area is within the integrated circuit substrate and interior to the first deep trench isolation structure. A second deep trench isolation structure is formed in the integrated circuit substrate about a perimeter of the storage capacitor area. The second deep trench isolation structure may serve to electrically isolate the storage capacitor area from the first, second, third, and fourth pixels.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: Jeffrey M. Raynor
  • Patent number: 10264667
    Abstract: The present disclosure is directed to a system that is configured to eject fluid vertically away from a thermal microfluidic die for use with scented oils or other fluids. The die is coupled to a rigid planar support board that separates the die from a reservoir of the fluid. The support board includes an opening that is lined with an inert liner that protects an interior surface of the support board from the fluid. The support board includes contact to an external power supply and contacts to the die on a first surface. The die is coupled to this first surface such that the second surface remains free of electrical connections.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.R.L., STMicroelectronics International N.V.
    Inventors: Simon Dodd, Joe Scheffelin, Dave Hunt, Steve Bush, Faiz Sherman
  • Patent number: 10261128
    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pramod Kumar, Vinay Kumar
  • Patent number: 10263603
    Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics International N.V.
    Inventors: Pascal Urard, Alok Kumar Tripathi
  • Patent number: 10263110
    Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Didier Dutartre, Pierre Morin, Francois Andrieu, Elise Baylac
  • Patent number: 10261702
    Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Patent number: 10263768
    Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Patent number: 10262898
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
  • Patent number: 10261175
    Abstract: A ranging apparatus includes a first array with first light sensitive detectors configured to receive light which has been reflected by an object and generate an output. A second array, spaced apart from the first array by a spacing distance, is further included, the second array having second light sensitive detectors. The second array is configurable to either receive light which has been reflected by the object or to be a reference array and generate an output. A processor operates to determine a distance to the object in response to the outputs from the first and the second arrays.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Patent number: 10264353
    Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O., STMicroelectronics (Alps) SAS
    Inventors: Jean Claude Bini, Dragos Davidescu, Igor Cesko, Jonathan Cottinet
  • Patent number: 10261117
    Abstract: A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics SA
    Inventors: Marc Houdebine, Sebastien Dedieu
  • Patent number: 10260876
    Abstract: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 16, 2019
    Assignee: STMICROELECTRONICS R&D (BEIJING) CO. LTD
    Inventors: Peng Fei Zhu, Yong Qiang Wu, Kai Feng Wang, Hong Xia Sun
  • Patent number: 10261252
    Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 16, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Guerber, Charles Baudot, Florian Domengie
  • Patent number: 10261912
    Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 16, 2019
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE
    Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
  • Patent number: 10264653
    Abstract: An apparatus includes an illumination source configured to emit light when driven with a current greater than a threshold current and driver circuitry configured to drive the illumination source with a controllable current. The driver circuit controlled by at least a first input value. At least one illumination detector is configured to detect light emitted by the illumination source and monitor circuitry is configured to receive an output from the illumination detector and provide the first input value.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 16, 2019
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: John Kevin Moore