Patents Assigned to STMicroelectronics AS
  • High doped III-V source/drain junctions for field effect transistors
    Patent number: 10256304
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 9, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Electrically pumped photonic crystal nanolaser
    Patent number: 10256604
    Abstract: A semiconductor nanolaser includes a rib formed by a stack of layers, in which stack central layers (33, 34, 35) forming an assembly of quantum wells are placed between a lower layer (32) of a first conductivity type and an upper layer (36) of a second conductivity type. Holes (42) are drilled right through the thickness of the rib, wherein the lower layer includes first extensions (38, 40) that extend laterally on either side of the rib, and that are coated with first metallizations (42, 44) that are located a distance away from the rib. The stack includes second extensions (45, 46) that extend longitudinally beyond said rib, and that are coated with second metallizations (47, 48).
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 9, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, Centre National de la Recherche Scientifique, Universite Paris Diderot
    Inventors: Guillaume Crosnier, Fabrice Raineri, Rama Raj, Paul Monnier
  • Selective power supply device for incandescent lamp or light-emitting diode
    Patent number: 10257917
    Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 9, 2019
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics S.r.l., STMicroelectronics Application GmbH
    Inventors: Philippe Sirito-Olivier, Giovanni Luca Torrisi, Manuel Gaertner, Fritz Burkhardt
  • PHOTONIC INTERCONNECTION SWITCHES AND NETWORK INTEGRATED IN AN OPTOELECTRONIC CHIP
    Publication number: 20190101699
    Abstract: A photonic interconnection elementary switch is integrated in an optoelectronic chip/The switch includes first and second linear optical waveguides which intersect to form a first intersection. Two first photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. Two second photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. A third linear optical waveguide is coupled to one of the first ring resonators and one of the second ring resonators. A fourth linear optical waveguide is coupled to another of the first resonators and to another of the second ring resonators. A base switch, complex switch, and photonic interconnection network integrated in an optoelectronic chip, include at least two of the photonic interconnection elementary switches.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas MICHIT, Patrick LE MAITRE
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20190103369
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Pascal FORNARA, Guilhem BOUTON, Mathieu LISART
  • DETECTION OF A TIME CONDITION RELATIVE TO A TWO-WIRE BUS
    Publication number: 20190102328
    Abstract: A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold value is stored in a memory and the measured value represents, in a first comparison, a longest duration of the low states of the synchronization signal.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francois TAILLIET
  • METHOD FOR FABRICATING AN ELECTRONIC DEVICE AND A STACKED ELECTRONIC DEVICE
    Publication number: 20190103368
    Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine SAXOD, Marika SORRIEUL
  • MEMS MIRROR DRIVEN BY DUAL PULSE DRIVE SIGNAL
    Publication number: 20190101744
    Abstract: Described herein is a device including mirror control circuitry for controlling a movable mirror. The mirror control circuitry includes drive circuitry for providing a drive signal to the movable mirror, and a processor. The processor cause the drive circuitry to generate the drive signal so as to have pulses with leading edges occurring an offset period of time after a maximum opening angle of the movable mirror and trailing edges occurring an offset period of time before a zero crossing of the movable mirror. The processor may sample a mirror sense signal from the movable mirror at times at which a derivative of capacitance of the movable mirror with respect to time is zero, and then perform an action based upon the samples.
    Type: Application
    Filed: October 2, 2017
    Publication date: April 4, 2019
    Applicant: STMicroelectronics Ltd
    Inventors: Sivan Kinstlich, Offir Duvdevany
  • Optical modulator having Mach-Zehnder diodes of reduced length
    Patent number: 10247967
    Abstract: A Mach-Zehnder modulator (MZM) includes a first optical path with a first diode coupled to a first voltage signal node and configured to modify a phase of a first light signal transmitted through the first optical path. A further diode is positioned in the first optical path and configured to introduce a phase shift to the first light signal. A second optical path includes a second diode coupled to a second voltage signal node and configured to modify a phase of a second light signal transmitted through the second optical path. A first voltage signal carried on the first voltage signal node and a second voltage signal carried on the second voltage signal node each vary between a reverse biasing voltage level and a forward biasing voltage level. An optical coupler is coupled to the first and second optical paths.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Valerie Danelon, Denis Pache
  • Configurable pseudo dual port architecture for use with single port SRAM
    Patent number: 10249363
    Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Harsh Rawat, Abhishek Pathak
  • Circuit and method for reading a memory cell of a non-volatile memory device
    Patent number: 10249373
    Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Campardo, Salvatore Polizzi
  • Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
    Patent number: 10249568
    Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Power transformer of the symmetric-asymmetric type with a fully-balanced topology
    Patent number: 10249427
    Abstract: A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics SA
    Inventor: Vincent Knopik
  • Inverse electrowetting energy harvesting and scavenging methods, circuits and systems
    Patent number: 10250163
    Abstract: An inverse electrowetting harvesting and scavenging circuit includes a first substrate having first and second surfaces. An electrode is formed proximate the first surface and includes an insulating layer covering a surface of the electrode. An electromechanical systems device includes a moveable mass extending over the first surface of the first substrate that may be displaced relative to the first substrate in three dimensions responsive to external forces applied to the moveable mass. The movable mass includes a moveable electrode and a conductive fluid is positioned between the insulating layer of the electrode and the movable electrode.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Sara Loi, Alberto Pagani
  • Method for compensating effects of substrate stresses in semiconductor devices, and corresponding device
    Patent number: 10250233
    Abstract: A semiconductor substrate includes a first portion and a second portion. The first portion of the substrate has a first deformation-stress sensor capable of supplying a first stress signal. The second portion of the substrate has a second deformation-stress sensor capable of supplying a second stress signal. The first stress signal and second stress signal are processed by a circuit to produce a compensation signal. The compensation signal is applied in feedback to one of the first and second stress signals to compensate for variations induced in said one of the first and second stress signals by stresses in the semiconductor substrate.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giuseppe Scilla
  • Manufacturing method for a fluid-ejection device, and fluid-ejection device
    Patent number: 10245834
    Abstract: A method for manufacturing a device for ejecting a fluid, including producing a nozzle plate including: forming a first nozzle cavity, having a first diameter, in a first semiconductor body; forming a hydrophilic layer at least in part in the first nozzle cavity; forming a structural layer on the hydrophilic layer; etching the structural layer to form a second nozzle cavity aligned to the first nozzle cavity in a fluid-ejection direction and having a second diameter larger than the first diameter; proceeding with etching of the structural layer for removing portions thereof in the first nozzle cavity, to reach the hydrophilic layer and arranged in fluid communication the first and second nozzle cavities; and coupling the nozzle plate with a chamber for containing the fluid.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mauro Cattaneo, Carlo Luigi Prelini, Lorenzo Colombo, Dino Faralli, Alessandra Sciutti, Lorenzo Tentori
  • Single-stage CMOS-based voltage quadrupler circuit
    Patent number: 10250133
    Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Network of electronic devices assembled on a flexible support and communication method
    Patent number: 10250301
    Abstract: Disclosed herein is an article including a garment, with a network formed on the garment. The network includes a main node with a main wired antenna, and at least one intermediate node with an intermediate wired antenna to be magnetically coupled to a respective device for that intermediate node. An electrical line electrically couples the main node to the at least one intermediate node. At least one electronic device is magnetically coupled to the intermediate wired antenna. A power supply unit is magnetically coupled to the main node via the main wired antenna thereof.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Apparatus for detecting the rotor position of an electric motor and related method
    Patent number: 10250172
    Abstract: An apparatus for detecting a position of a rotor of a DC motor with N phases having a plurality of windings. The apparatus includes circuitry to couple at least two of the windings between a supply voltage and a reference voltage according to a first current path and allow the current stored in the two windings to be discharged through a second current path. The circuitry is configured to force the at least two windings at a short circuit condition in the second current path. The apparatus also includes a measurement circuit configured to measure the time period of discharging the current stored in the two windings and a rotor position detector for detecting the rotor position based on the measured time period.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Michele Boscolo Berto
  • Hybrid photonic and electronic integrated circuits
    Patent number: 10247881
    Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang