Abstract: A stepper motor is driven according to step driving modes including a full-step driving mode, a half-step driving mode and micro-stepping modes. The stepper motor may also be driven in an acceleration phase. A method of controlling the stepper motor includes controlling the current step driving mode of the motor by a processing unit. During the acceleration phase of the stepper motor and the stepper motor being in driven in a current step driving mode other than the full-step driving mode, the processing unit tests, after each speed increase, if a remaining computing power of the processing unit is sufficient for control of the stepper motor to remain in the current step driving mode, and if not the processing unit, in presence of a first switching condition, switches control of the stepper motor to the driving mode having the closest coarser step.

Abstract: An alternating current (AC) drive signal having a first frequency and a high logic level at a boosted supply voltage is applied to drive a capacitive sensing line of a capacitive touch panel. The boosted supply voltage is generated by boosting an input voltage. The voltage boosting is effectuate by a charge pump circuit operating synchronous to assertion of the AC drive signal with a charge transfer time that is adaptable to different capacitive load conditions.

Abstract: A circuit for amplifying signals from a Micro Electro-Mechanical System (MEMS) capacitive sensor is provided. First and second input nodes receive a sensing signal applied differentially between the input nodes. A first amplifier stage and a second amplifier stage, respectively, produce a differential output signal between first and second output nodes. A common mode signal is detected at the output nodes. A voltage divider having an intermediate tap node is coupled between the first output node and the second output node. A feedback stage is coupled between the tap node of the voltage divider and the inputs of the first amplifier stage and the second amplifier stage, where the feedback line is sensitive to the common mode signal at the output nodes.

Abstract: A method for adapting an antenna circuit including at least one first capacitive element and an inductive element in series, and at least one second capacitive element having a first electrode connected between the first capacitive element and the inductive element, wherein data representative of the voltage of said first electrode are applied to the second electrode of the second capacitive element.

Abstract: A circuit includes a timer circuit configured to generate a first control signal defining a first time period and a second control signal defining a second time period. A controller is configured to control a high-side and a low-side transistor of a half-bridge circuit in response to the first and second control signals only during a first switching cycle of the half-bridge circuit. The half-bridge circuit includes a bootstrap capacitor coupled to a node between the high-side and low-side transistors. The controller turns on the low-side transistor for the first time period during the first switching cycle and configured turns off the low-side and the high-side transistors for the second time period during the first switching cycle.

Abstract: A driving module of a resonant converter receives an enabling signal and a voltage across a switch of a secondary side, and generates a control signal for first and second switches of the secondary side. The driving module cyclically controls switches of a primary full-bridge switching stage and both switches of the secondary side. After a fixed time, the driving module turns off the low-side switch and turns on the high-side switch, waits for a rising edge of the enabling signal, waits for zero current in the secondary side switches, turns off the first switch via the control signal after a variable delay relative to the rising edge of the enabling signal, keeps the second switch on, waits for zero voltage across the first switch, switches back on the first switch via the control signal when the voltage measured across the first switch drops below a variable threshold.

Abstract: A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to receive a corresponding write address. The circuit may also include an output data bus, and an address protection circuit coupled to the input data, address, and output data buses and configured to generate an address protection value based on the corresponding write address, and generate modified write data, on the output data bus. The modified write data includes the write data and the address protection value. The output data bus may have a width greater than a width of the input data bus.

Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

Abstract: A case includes a base for receiving a portable phone and a flap hinged to the base and including a housing configured to receive a microcircuit card. A first contactless communication antenna is provided in the flap for coupling to an antenna of the microcircuit card. A second contactless communication antenna is provided in the base for coupling to an antenna of the portable phone. The first and second first contactless communication antennae are electrically connected to each other.

Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.

Abstract: Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

Abstract: An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract: A semiconductor on insulator substrate includes a semiconductor support layer, a buried insulating layer over the semiconductor support layer and an epitaxial semiconductor layer over the buried insulating layer. A deep trench isolation penetrates completely through the epitaxial semiconductor layer to the buried insulating layer to electrically insulate a first region of the epitaxial semiconductor layer from a second region of the epitaxial semiconductor layer. A single photon avalanche diode (SPAD) includes an anode formed by the first region of the epitaxial semiconductor layer and a cathode formed by a well located within the first region of the epitaxial semiconductor layer. An ancillary circuit for the SPAD is located in the second region of the epitaxial semiconductor layer and electrically coupled to the SPAD.

Abstract: Device, comprising a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

Abstract: A method and apparatus for determining the attitude of an object is provided herein. The method for determining the attitude of the object comprises: receiving a gravity acceleration signal and a geomagnetic field signal, the gravity acceleration signal and the geomagnetic field signal changing with the attitude of the object accordingly; determining a gravity field representation in an object coordinate system according to the gravity acceleration signal, and determining a geomagnetic field representation in the object coordinate system according to the geomagnetic field signal; calculating a conversion parameter of coordinate system between to the object coordinate system and a terrestrial coordinate system according to the gravity field representation and the geomagnetic field representation in the object coordinate system; and determining the attitude of the object according to the conversion parameter of coordinate system.

Abstract: A method includes preparing a first histogram from the emission of initial optical radiation and including at least one processing iteration performed at a rate of a clock signal having an internal period equal to a sub-multiple of the optical period a sensor signal and a reference signal. Successive iterations of histogram preparation are performed so that in each iteration a time shift of the initial optical radiation is provided by a first fraction of the internal period until at least one portion of the internal period is covered to obtain an additional histogram at the conclusion of each iteration. A numerical combination of the first histogram and additional histograms is performed to obtain a final histogram having a finer time granularity than that of the first histogram.

Abstract: A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.