Patents Assigned to STMicroelectronics AS
  • Patent number: 10242862
    Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing—rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Patent number: 10243356
    Abstract: A device may be for protection against overvoltages in a power supply line. The device may include a breakover diode, an avalanche diode coupled in series with the breakover diode, and a switch coupled in parallel with the breakover diode and the avalanche diode. The device may also include a circuit coupled across the avalanche diode and configured to control the switch.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (TOURS) SAS
    Inventors: Jérôme Heurtier, Guillaume Bougrine, Mathieu Rouviere
  • Patent number: 10239748
    Abstract: A microelectromechanical device includes: a substrate; a semiconductor die, bonded to the substrate and incorporating a microstructure; an adhesive film layer between the die and the substrate; and a protective layer between the die and the adhesive film layer. The protective layer has apertures, and the adhesive film layer adheres to the die through the apertures of the protective layer.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luca Maggi, Sebastiano Conti
  • Patent number: 10242303
    Abstract: In an embodiment, a carrier signal generation circuit can be used for a Radio-frequency identification (RFID) transponder device. A frequency divider circuit has a first input to receive a first frequency signal, a second input to receive a division ratio signal, and an output to provide a carrier signal as a function of the first frequency signal and the division ratio signal. A phase difference circuit has a first input to receive an analog reader device carrier signal, a second input to receive a signal based on the first frequency signal and an output to provide a digital phase difference signal as a function of the reader device carrier signal and the signal based on the first frequency signal. A signal processor has an input coupled to the output of the phase difference circuit.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 26, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Vinko Kunc, Iztok Bratuz, Albin Pevec, Kosta Kovacic, Maksimiljan Stiglic
  • Patent number: 10242272
    Abstract: A sequence of images obtained by a camera mounted on a vehicle is processed in order to generate Optical Flow data including a list of Motion Vectors being associated with respective features in the sequence of images. The Optical Flow data is analyzed to calculate a Vanishing Point by calculating the mean point of all intersections of straight lines passing through motion vectors lying in a road. An Horizontal Filter subset is determined taking into account the Vanishing Point and a Bound Box list from a previous frame in order to filter from the Optical Flow the horizontal motion vectors. The subset of Optical Flow is clustered to generate the Bound Box list retrieving the moving objects in a scene. The Bound Box list is sent to an Alert Generation device and an output video shows the input scene where the detected moving objects are surrounded by a Bounding Box.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Spampinato, Salvatore Curti, Nunziata Ivana Guarneri, Arcangelo Ranieri Bruna
  • Patent number: 10244638
    Abstract: A proximity sensor is provided according to the embodiments of the present disclosure, comprising: a sensor chip; a light-emitting device; a substrate, the sensor chip and the light-emitting device being located on the substrate; a transparent molding material covering a light-emitting surface of the light-emitting device; and a non-transparent molding material separating the transparent molding material from the sensor chip.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 26, 2019
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 10243728
    Abstract: A method of verifying the sensitivity of an electronic circuit executing a Rijndael-type algorithm to side channel attacks, wherein: each block of data to be encrypted or to be decrypted is masked with a first mask before a non-linear block substitution operation is applied based on a substitution box, and is then unmasked with a second mask after the substitution; the substitution box is recalculated, block by block, before the non-linear operation is applied, the processing order of the blocks of the substitution box being submitted to a permutation; and a side channel attack is performed on the steps of recalculating, block by block, the substitution box.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 26, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nicolas Bruneau
  • Patent number: 10243545
    Abstract: Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Beng-Heng Goh, Yi Ren Chin
  • Patent number: 10243470
    Abstract: A control circuit for an electronic converter having a power stage controls the operation of a power stage as a function of a feedback control signal that indicates an input power provided to the power stage. The control circuit generates a digital reference signal as a function of the feedback control signal and a first signal based on an input voltage supplied to the power stage. The control circuit generates a modified control signal as a function of the digital reference signal and a second signal based on an input current supplied to the power stage.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Claudio Adragna
  • Patent number: 10241322
    Abstract: A control device for controlling a switching converter includes a switch controller that generates a control signal with a switching period for controlling switching of a switch of the switching converter and setting a first interval in which a current flows in the switch, a second interval in which energy is transferred onto a storage element of the switching converter, and a third, wait, interval, at the end of the second interval. The duration of the first interval is determined based on a control voltage indicating the output voltage. A pre-distortion stage receives the control voltage and generates a pre-distorted control voltage as a function of the control voltage and a relationship between one of the first and third time intervals and the switching period, wherein the switch controller is configured to control a duration of the first interval based on the pre-distorted control voltage.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Gritti, Claudio Adragna
  • Patent number: 10243550
    Abstract: An electronic device includes a power switch having a control terminal coupled to a first node, a first conduction terminal coupled to a second node, and a second conduction terminal coupled to a third node. A monitoring circuit has a first input coupled to the first node and a second input coupled to the second node, the monitoring circuit to generate a monitor signal indicating gate oxide stress on the power switch as a function of first and second voltages received at the first and second inputs thereof. A protection circuit actuates to protect the power switch from the gate oxide stress when the monitor signal indicates the gate oxide stress on the power switch. The monitoring signal is generated based upon a comparison of currents generated based upon the voltages at the first and second node, as well as a current generated based upon a programmable reference voltage.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Pavan Nallamothu
  • Patent number: 10243543
    Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jean Nicolai, Albert Martinez
  • Patent number: 10243617
    Abstract: A coupling circuit for power line communications includes a coupling transformer having first and second mutually coupled windings, with the first winding connectable to a power line. The second winding includes a pair of intermediate taps with one or more tuning inductor therebetween. The inductor or inductors are set between a first portion and a second portion of the second winding of the coupling transformer. A switch member is provided coupled with the inductor. The switch member is selectively actuatable to short-circuit the inductor.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Riccardo Fiorelli
  • Patent number: 10243074
    Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 26, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10242944
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20190087035
    Abstract: Disclosed herein is a method of operating a touch screen controller in a device with a touch screen having force lines and sense lines. The method includes receiving touch data from the touch screen, and operating the touch screen in a self capacitance sensing mode. In the self capacitance sensing mode, which force lines have strength values indicating a potential touch to the touch screen are determined. The method also includes operating the touch screen in a mutual capacitance sensing mode, and in the mutual capacitance sensing mode, performing mutual capacitance sensing on only a subset of the force lines, with the subset of the force lines including at least those force lines indicating the potential touch to the touch screen.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 21, 2019
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Abe Yun, Aiden Jeon, Glen Kang
  • Publication number: 20190086519
    Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Boris Rodrigues Goncalves, Marie Guillon, Yvon Cazaux, Benoit Giffard
  • Publication number: 20190088695
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Publication number: 20190086474
    Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Srinivas Dhulipalla
  • Publication number: 20190088562
    Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 21, 2019
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Malta) Ltd
    Inventors: Jerome LOPEZ, Roseanne DUCA