Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.

Abstract: A microfluidic device, having a containment body accommodating a plurality of ejecting elements arranged adjacent to each other. Each ejecting element has a liquid inlet, a containment chamber, a piezoelectric actuator and an ejection nozzle. The piezoelectric actuators of each ejecting element are connected to a control unit configured to generate actuation signals and to be integrated in the containment body.

Abstract: A distributed active transformer includes an input transformer set and an output transformer set. Active stages are coupled between a transformer in the input transformer set and a transformer in the output transformer set. The input and output transformer sets are each configured as a slab transformer. The input slab transformer includes a single primary slab and many secondary slabs. The output slab transformer includes many primary slabs and a single secondary slab.

Abstract: An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.

Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.

Abstract: Disclosed herein is an electronic device including a first laser source configured to project a first laser beam, and a second laser source configured to project a second laser beam in alignment with the first laser beam in a first direction but at an angle with respect to the first laser beam in a second direction. A mirror apparatus is positioned so as to reflect the first and second laser beams. Control circuitry is configured to control the mirror apparatus to simultaneously reflect the first and second laser beams in a first scan pattern to form an first image, the first image formed from the first scan pattern having a number of scan lines greater than two times a horizontal resonance frequency at which the mirror apparatus oscillates divided by a desired frame rate of the first image.

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.

Abstract: A receiver for digital signals includes a radiofrequency stage. A feedback loop controls a variable attenuation resistance applied to a modulated radiofrequency signal passing through the radiofrequency stage as a function of a comparison of an amplitude of the modulated radiofrequency signal with a reference value. A baseband stage includes an RC network cascaded to the radiofrequency stage and coupled to a baseband detector that generates the baseband signal. The feedback loop includes a circuit for detecting a range of variation of the comparison. The value of the variable resistance is controlled as a function of an end value (e.g., maximum or minimum) of the detected range of variation.

Abstract: An integrated electronic device having a semiconductor body including: a first electrode region having a first type of conductivity; and a second electrode region having a second type of conductivity, which forms a junction with the first electrode region. The integrated electronic device further includes a nanostructured semiconductor region, which extends in one of the first and second electrode regions.

Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.

Abstract: A control module controls a switching converter including at least one inductor element and one switching element. The module includes: a driver circuit that generates a control signal which controls the on and off cycles of the switching element; a first modulation circuit which sends a command to the driver circuit in such a manner as to generate edges of a first type of the control signal, as a function of the input electrical quantity and of a reference electrical quantity; and a second modulation circuit which sends a command to the driver circuit in such a manner as to generate edges of a second type of the control signal, as a function of a first and a second internal electrical quantity, which are functions respectively of the charges on a first and a second capacitor, which are charged and discharged as a function of the control signal.

Abstract: A photonic interconnect switch is formed by first and second linear optical waveguides that cross to form an intersection. First and second redirecting photonic ring resonators are coupled together in an intermediate optical coupling zone and are controllable with an electrical signal. The first ring resonator is coupled to the first optical waveguide in a first optical coupling zone. The second ring resonator is coupled to the second optical waveguide in a second optical coupling zone.

Abstract: An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via its rear face is formed by a p-n junction that is biased into conduction. Thinning of the substrate is detected by monitoring a current flowing through the p-n junction, and comparing that current to a threshold. In the event the compared current indicates no thinning of the semiconductor substrate, the circuitry for biasing and comparing is deactivated.

Abstract: In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then enciphered and communicated back to host device when a decision on product authenticity is made.

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.

Abstract: Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to optical inspection. An electrical wafer sort is performed to test the integrated functional circuitry of each die. The array of fuse elements for each die on the wafer are programmed through the electrical wafer sort process with data bits defining a die identification that specifies a location of the die on the wafer. The die is then encapsulated in a package. In the event of package failure, a decapsulation is performed to access the die. Optical inspection of the array of fuse elements is then made to extract the die identification.

Abstract: A method of protecting a modular exponentiation calculation executed by an electronic circuit using a first register and a second register, successively comprising, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of said other one of the registers is stored in a third register before the first step and is restored in said other one of the registers before the second step.

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.