Abstract: A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A method for converting a rectilinear image and a focal length into a cylindrical image parameterized by a height of the cylinder and an angular distance in a single buffer on a remote processing device. The method, on the remote processing device, comprising joining two or more images together to form a panoramic image with corrected perspective. The rectilinear transformation is “in-place” and requires only one buffer. Color correction and motion estimation is also carried out on the remote device. In an alternate embodiment, a computer readable medium corresponding to the above method is described.

Abstract: A disk drive having a motor and a velocity control loop, which includes a frequency detector and a filter. The filter includes a filter section and an accumulator. The filter is programmable in that filter coefficient(s) are dynamically received by the filter section. One embodiment of the filter section is an infinite impulse response filter. One embodiment of the filter is a digital integrated circuit. A method for compensating a control loop by infinite impulse response filtering and accumulating. The control loop may be a position, velocity, acceleration or force control loop. A programmable digital integrated circuit for compensating a velocity control loop having a filter section cascaded with an accumulator. The integrated circuit may include memory for storing filter coefficient(s) for the filter section, thereby not requiring external components.

Abstract: A structure and method for creating an integrated circuit passivation structure including, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: A system and method are disclosed for providing error correction coding having a selectively variable degree of redundancy. The system and method include generating extended check symbols by performing a Reed-Solomon operation on unused check symbols that do not form a portion of an interleaved code word. An extended check symbol is generated from the unused check symbols appearing in a column of the unused check symbols. The extended check symbols are stored with the interleaved code words in a data storage device. The extended check symbols are retrieved from the data storage device with the corresponding interleaved code words. Following the decoding of the interleaved code words and the identification of uncorrectable errors therein, the extended check symbols are decoded to recover the corresponding unused check symbols for the previously uncorrectable interleaved code words.

Abstract: An integrated circuit includes storage circuits comprising isolation transistors to which a certain bias voltage may be applied. The bias voltage is generated by a bias voltage generator. A boost circuit responds to initial bias voltage transition by generating a boost current that is applied to the isolation transistors with the transitioning bias voltage.

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract: A method for exposed die molding for integrated circuit packaging is provided that includes providing a mold comprising an upper mold with a flexible material, a lower mold, and a floating plunger. A substrate of an integrated circuit structure is clamped between the upper mold and the lower mold. An integrated circuit die of the integrated circuit structure is clamped between the floating plunger and the upper mold through the flexible material.

Abstract: The probe card of the present invention permits testing of a semiconductor device-under-test under high temperatures and includes a plurality of printed circuit boards stacked together to form a probe interface board having a top surface and a lower testing face. A heat sink is mounted on the probe interface board at the top surface and extends to the lower testing face. A needle supporting module is carried by the heat sink at the lower testing face and has a plurality of probe needles for electrically connecting to electrical contacts of a semiconductor device-under-test.

Abstract: A synchronizer circuit includes an input terminal, an output terminal, and a recovery circuit coupled to the input and output terminals. The input terminal receives an input signal that includes a sync mark, and the recovery circuit is operable to recover the sync mark from the input signal and to generate a synchronization signal on the output terminal in response to the recovered synchronization mark. For example, such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a Viterbi detector that is separate from the circuit. By performing the sync-recovery function in a separate circuit, one can reduce the complexity and increase the data-recovery speed of the Viterbi detector. Furthermore, the synchronizer circuit can recover the sync mark by executing state-transition routines in alignment with the input signal. For example, one can align the synchronizer circuit's state-transition routines to the preamble of the read signal.

Abstract: A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and complement signals in the same deasserting logical state for a predetermined period of time prior to asserting either the logical true signal or the logical complement signal, in response to a signal edge transition appearing on the address input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the logical true and complement signals.

Abstract: A circuit that synchronizes an output clock signal to a second clock signal includes a frequency locked loop circuit that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output signal clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal.

Abstract: Passivation for capacitive sensor circuits, which overlies the capacitive sensor electrodes and is normally conformal to the electrodes and the underlying interlevel dielectric, is planarized by forming a layer of flowable oxide over the electrodes before forming the passivation. The flowable oxide, which is preferably very thin over the electrodes to minimize loss of sensitivity, provides a substantially planar upper surface, so that passivation formed on the flowable oxide is also substantially planar. Alternatively, a deposited oxide planarized by chemical mechanical polishing may be employed to planarize the surface on which a passivation stack is formed. The planarized passivation provides markedly improved scratch resistance.

Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.

Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and too discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK1 and CLK2, where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START1 and START2 (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.

Abstract: A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface for receiving a first bus access request signal from a first bus device; 2) a delay circuit that receives the first bus access request signal from the input interface and generates a time-delayed first bus access request signal; and 3) a comparator circuit that receives the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generates a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled. The comparator circuit disables the line driver enable signal if either of the first bus access request signal or the time-delayed first bus access request signal is disabled.

Abstract: A system and method is disclosed for using a pre-formed film in a transfer molding process of the type that uses a transfer mold to encapsulate portions of an integrated circuit with a molding compound. A film of compliant material is pre-formed to conform the shape of the film to a mold cavity surface of the transfer mold. The pre-formed film is then placed adjacent to the surfaces of the mold cavity of the transfer mold. The mold cavity is filled with molding compound and the integrated circuit is encapsulated. The pre-formation of the film allows materials to be used that are not suitable for use with prior art methods.

Abstract: An embodiment of the present invention includes a method for driving a voice coil motor in response to signals from a feedback network that senses voice coil motor velocity. The method includes steps of providing a drive signal to an H-bridge for a first interval. At the end of the first interval, the H-bridge is placed in a high impedance state. Following a pause for a second interval during which transient voltages extinguish, a sample and hold circuit is coupled to the voice coil motor. The sample and hold circuit measures a voltage from the voice coil motor that is directly proportional to voice coil motor velocity and thus is directly related to head velocity. After the sample and hold circuit measures the voice coil motor voltage, the input to the sample and hold circuit is disabled. An output signal from the sample and hold circuit is coupled to the feedback network and thus to the H-bridge.