Abstract: An image processing system which processes, in real time, multiple images, which are different views of the same object, of video data in order to match features in the images to support 3 dimensional motion picture production. The different images are captured by multiple cameras, processed by digital processing equipment to identify features and perform preliminary, two-view feature matching. The image data and matched feature point definitions are communicated to an adjacent camera to support at least two image matching. The matched feature point data are then transferred to a central computer, which performs a multiple-view correspondence between all of the images.

Abstract: A two-step motion prediction for MPEG-2 interpolation case-D will yield visual artifacts if not corrected. An improved MPEG-2 decoder includes a logic gate, multiplexer, and adder. When both the horizontal (h0) and vertical (h1) motion vector components require a half pixel interpolation (case-D), the multiplexer forwards the constant minus three to the adder, otherwise a constant zero is used. Such adder modifies the DC coefficient input to the inverse discrete cosine transformer to include a correction term for the predicted pixels calculated by a two-step predictor. A correction value of −0.375 is evenly distributed over all sixty-four resulting spatial coefficients during the inverse discrete cosine transform. This results statistically in a slightly brighter set of correction terms. Such offsets result in a slightly darker prediction that is formed by the two-step predictor. The output frames are statistically correct images.

Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identifies the addressed column of memory cells as being defective.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response.

Abstract: A method, apparatus, computer implemented method and computer programmed product for recovering data from a split sector associated with an inoperable servo timing mark. Instead of using a servo timing mark to synchronize the read/write head to the spin speed variation of a storage media, the trailing end of the data fragment preceding the inoperable servo timing mark is used as a reference point. After detecting the reference point, the read operation is halted a predetermined delay time after which the read operation is resumed recovering the data from the sector relying on the inoperable servo timing mark.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: A system and method for selecting between two biasing modes for biasing magneto resistive heads in a disk drive. A mode selector selects either a voltage biasing circuit or a current biasing to supply the bias voltage or bias current, respectively, to a magneto resistive head. The selection can be based on changes in parameters in the disk drive or magneto resistive heads during disk drive operation.

Abstract: A circuit and method are disclosed for monitoring the voltage level of an electrical signal, such as an unregulated power supply. The circuit includes a comparator that compares the electrical to the voltage reference and generates an output having a value that is based upon the comparison. A oscillation suppression circuit receives the output of the comparator and generates an output signal that follows the output of the comparator once the output of the comparator remains stable and in the same logic state for a predetermined of time.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: A user configurable dual bank memory device is disclosed. The memory device includes a plurality of core banks of memory cells and a set of storage elements having stored therein configuration information. The configuration may be used to configure or group core banks of memory cells together to form a dual bank memory device. The memory device includes control circuitry for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further includes a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second set of sense amplifiers dedicated to performing sense amplification only during memory modify operations.

Abstract: An image processing system recovers 3-D depth information for pixels of a base image representing a view of a scene. The system detects a plurality of pixels in a base image that represents a first view of a scene. The system the determines 3-D depth of the plurality of pixels in the base image by matching correspondence to a plurality of pixels in a plurality of images representing a plurality of views of the scene. The system then traces pixels in a virtual piecewise continuous depth surface by spatial propagation starting from the detected pixels in the base image by using the matching and corresponding plurality of pixels in the plurality of images to create the virtual piecewise continuous depth surface viewed from the base image, each successfully traced pixel being associated with a depth in the scene viewed from the base image.

Abstract: A thermal ink jet printhead system has a printhead with base member and a plurality of ink flow channels formed in the base member that connect to an ink reservoir and terminate in a nozzle through which ink is expelled. A heating element is associated with each ink flow channel. A monolithically integrated multiple output power driver circuit is formed as a semiconductor integrated circuit and connected to each heating element in the printhead. The multiple output driver circuit includes a power MOS transistor connected to each heating element. A reference circuit is operatively connected to each gate of the power MOS transistor and includes a reference transistor having a gate and a reference amplifier that receives as inputs a reference voltage and a source of current. An amplifier output is operatively connected to the gates of the power output transistors and the gate of the reference transistor.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. The transaction interface uses information derived from the data packets received to form message control blocks, particular for each individual task, and places the control blocks into the proper task queue. The transaction interface forms a dispatcher message control block and places it into the scheduler/dispatcher queue to initiate the task. If there are no other message control blocks in the queue particular for the called task, the called task is immediately started. Otherwise, the message control block waits in the queue to eventually be operated on.

Abstract: Minute surface damage or irregularities on the sensing surface of a capacitive sensor integrated circuit is detected by acquiring a preliminary image of the capacitance readings for the sensor array, coating the sensing surface with an electrolyte solution, then acquiring an additional image while the sensing surface is coated and/or after the electrolyte solution is removed. The electrolyte solution accelerates manifestation of pixel degradation or failure caused by surface damage or irregularities. Defective regions are identified by change of grayscale pixels in the preliminary image while the electrolyte coating is on the sensing surface and then again after the electrolyte coating is removed.

Abstract: A method and apparatus is disclosed for communicating with a host. In one embodiment, a smart card has an IC with voltage conditioning circuitry and a pull-up resistor. The smart card, when inserted in a smart card reader coupled to the host, is capable of signaling the host over a bus using the pull-up resistor selectively coupled to a voltage output of the voltage conditioning circuitry and a first output of the smart card. The voltage conditioning circuitry output is selectively coupled to the first output through the resistor, responsive to the device being powered by the bus but not transmitting. This tends to pull up the first output to the voltage level of the voltage source, which makes the smart card capable of being properly detected by the host upon the bus being driven by a host. Selectively disconnecting the pull-up resistor while the smart card is transmitting or receiving results in a more balanced differential output signal.

Abstract: A method and ethernet device is disclosed and includes an extended FIFO buffer. The link partner within the ethernet system is in communication with data terminal equipment (DTE). The speed of the link partner determined using a first packet received within the FIFO buffer. Subsequent FIFO buffer reading is optimized based on the determined speed of the link partner, thus for enhancing the inter-packet gap space usage.

Abstract: A method and system are disclosed for spinning the spindle motor of a disk drive from a stationary state to an operable state that is suitable for performing a memory access operation. The method and system include energizing the polyphase motor in a first predetermined commutation phase; detecting whether a zero crossing of a back electromotive force (bemf) signal corresponding to the first predetermined commutation phase occurs; sensing whether the polyphase motor advanced to a next successive commutation phase relative to the first predetermined commutation phase; and performing an acceleration procedure to accelerate the speed of the polyphase motor towards a desired speed based upon a detected zero crossing of the bemf signal and an affirmative determination that the polyphase motor advanced to a next successive commutation phase relative to the first predetermined commutation phase.

Abstract: An apparatus (and method) is provided that pumps (up or down) the voltage on a memory cell thereby increasing (above the logic one voltage value) or decreasing (below the logic zero voltage value) the voltage stored in the memory cell, and providing an increased differential on the bit lines during a subsequent read operation of the memory cell. When a logic one or zero voltage is coupled to the first plate of the memory cell for storage, the second plate is held at a voltage that is lower or higher, respectively (preferably a voltage that is the complement logic value of the value being stored). After the word line is deactivated (thereby decoupling the memory cell from the bit line and storing a logic one voltage value or logic zero voltage value), the voltage on the second plate is correspondently either raised or lowered. In the present invention, the second plate is raised or lowered to the precharge and equilibrate value (usually Vdd/2).