Abstract: A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: A method and system of scaling images on a video display is disclosed. A video data stream is processed into video data, which is displayed on a video display at a predetermined aspect ratio. A user manipulable controller, such as a joystick, is operative with a graphics processor unit for scaling images on the video display by obtaining video source values of pixel width and height to be displayed and determining the smallest integer increment on the x/y axis that will maintain the desired aspect ratio using a greatest common denominator to reduce the ratio to the lowest integer.

Abstract: An integrated heater formed as a field effect transistor in a semiconductor substrate, with the transistor having source and drain regions with a channel region extending therebetween to conduct current. The channel region has a resistance when conducting current to generate heat above a selected threshold. A dielectric layer is disposed on the channel region and a gate electrode is disposed on the dielectric layer to control the current of the channel region. A thermally insulating barrier may be formed in the semiconductor material extending about the transistor. The object to be heated is positioned to receive the heat generated by the resistance of the channel region; the object may be a fluid chamber.

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated.

Abstract: A method, system and computer readable medium for transforming three dimensional (3D) color information into a color standard is described. A 3D cube defined by eight RGB color points representing the eight vertices of the 3D cube is stored. Each of the eight points represents one of the colors: red, yellow, white, magenta, blue, black, green and cyan. In addition, each of the eight points represents the difference between the capacity of a display and the color standard. The 3D cube is divided into six tetrahedrons and the tetrahedron corresponding to an input RGB pixel is selected. A 3×3 matrix based on the vertices of the selected tetrahedron is calculated. The 3×3 matrix is then multiplied by the components of the input RGB pixel to produce an output RGB pixel conforming to the color standard.

Abstract: A device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device has a differential amplifier configuration having an input to receive a comparison signal, a plurality of inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also has at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal.

Abstract: A method, and a system for implementing such method, for use in a magnetic disk storage system for compensating for variation in spin speed of a data storage media from a nominal or design spin speed. The method includes providing the nominal spin speed for the data storage media in the particular magnetic disk storage system and then measuring the actual spin speed of the data storage media. In one preferred embodiment, the spin speed measurement is completed by measuring the time from one servo position field to the next sequential servo position field in a track on the data storage media. Next, the present spin speed variation is determined by comparing the measured spin speed with the nominal spin speed. A correction factor is calculated based on the spin speed error and applied to at least one data transfer parameter, such as channel reference frequency or read/write gate assertion timing, prior to a subsequent data transfer process (i.e., a read or a write operation).

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.

Abstract: To optimize the performance of DSL modems in the same cable bundle, the size and position of the bandwidth used for transmission is intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated. Additionally, by intelligently selecting the position of the used bandwidth within the total available bandwidth, near-end crosstalk (NEXT) noise within the cable bundle may be minimized.

Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

Abstract: The invention provides a method and apparatus for optimizing instruction prefetch and caching in a processor. In the preferred embodiment, a path prediction circuit maintains information about which cache lines are likely to be executed in the future. This information is used to independently fetch the predicted cache lines, store them in a prefetch queue, and load them in to the instruction cache as instructions contained in these lines are about to be decoded by the processor. A plurality of cache lines can be in the process of being simultaneously fetched from main memory to load the prefetch queue.

Abstract: A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack.

Abstract: A scanning fingerprint detection system includes an array of capacitive sensing elements, the array having a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has first and second conductor plates connected across an inverting amplifier, the conductor plates forming capacitors with the ridges and valleys of a fingerprint of a finger pressed against a protective coating above the array, the inverting amplifier generating a signal indicative of a ridge or valley. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image.

Abstract: Fast and efficient photodiodes with different structures are fabricated using CMOS process technology by adapting transistor structures to form the diode structures. The anode regions of the photodiodes correspond to either PLDD regions of PMOS transistors or P-wells of NMOS transistors to provide two different photodiode structures with different anode region depths and thus different drift region thicknesses. An antireflective film used on the silicon surface of the photodiodes is employed as a silicide-blocking mask at other locations of the device.

Abstract: The present invention relates to a device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device comprises a differential amplifier configuration having an input to receive a comparison signal, a plurality inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also comprises at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal. Finally, this device incorporates at least one plurality of latches each having at least one input terminal connected to a corresponding output of the differential amplifier configuration and at least one drive terminal coupled to the output terminal of the logic circuit with each of said latch circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A method, system and computer readable medium for providing targeted advertising during execution of an application is described. A server system assembles an application including 3D objects and advertising texture maps directed towards a demographic. The application is then provided for download over a network to a client system, which belongs to the demographic. The client system then executes the application, which maps the texture maps onto the 3D objects during execution. The client system displays the 3D objects during execution of the application. The server system sends periodic updates consisting of texture maps to the client system. The client system maps the updated texture maps onto the 3D objects during execution.

Abstract: A current amplifier comprising an amplifier circuit with overall negative feedback and an output current amplification circuit. In one embodiment, a photodiode provides a current to be amplified and the amplifier circuit and the output current amplification circuit are implemented using MOS technology.

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA.