Patents Assigned to STMicroelectronics, Inc.
  • Non-linear adaptive image filter for filtering noise such as blocking artifacts
    Patent number: 6600839
    Abstract: A filter reduces artifacts, such as grid noise and staircase noise, in block-coded digital images with image block boundaries. The type of filtering is determined after an estimation of the image global metrics and local metrics. For areas of the image near grid noise, the filter performs low pass filtering. For image fine details, such as edges and texture, no filtering is performed so that masking is avoided. The filter operates in intra-field mode and uses a fuzzy logic process, pixel deltas, and dual ramp generators to determine the horizontal and vertical length of a processing window surrounding an image block boundary.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: July 29, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Massino Mancuso, Antonio Maria Bornco
  • System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package
    Patent number: 6600227
    Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential build up layers that may be placed on a sequential build up substrate.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: July 29, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony M. Chiu, Harry Michael Siegel
  • Fingerprint sensor power management detection of overcurrent
    Patent number: 6597289
    Abstract: A power management unit monitors current drawn by a fingerprint sensor circuit and generates a “heartbeat” signal during normal operation. If a latchup event occurs, with attendant increase in current drawn by the fingerprint sensor circuitry, the heartbeat signal terminates and an interrupt is subsequently triggered to start a latchup recovery routine. Power to the fingerprint sensor circuitry is switched off and the interrupt is then cleared by writing appropriate values to control bits within the power management register.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: July 22, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: Marco Sabatini
  • Method and apparatus for detecting motion of a motor for a disk drive system
    Patent number: 6598000
    Abstract: A method and apparatus are disclosed for controlling the operation of a polyphase motor, and particularly to determining whether the motor is spinning. The method and apparatus include initially sensing an electrical characteristic of a single phase winding of the motor. Having sensed values of the electrical characteristic, a determination is made as to whether or not the motor's rotor is spinning. Upon a determination that the rotor is not spinning, a spin-up operation is performed to bring the spin of the rotor to operable spin speeds. Otherwise, a resynchronization operation is performed.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: July 22, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Paolo Menegoli, Ender T. Eroglu, Whitney H. Li
  • Flexible galois field multiplier
    Publication number: 20030135530
    Abstract: A flexible Galois Field multiplier is provided which implements multiplication of two elements within a finite field defined by a degree and generator polynomial. One preferred embodiment provides a method for multiplying two elements of a finite field. According to the method, two input operands are mapped into a composite finite field, an initial KOA processing is performed upon the two operands in order to prepare the two operands for a multiplication in the ground field, the multiplication in the ground field is performed through the use of a triangular basis multiplier, and final KOA3 processing and optional modulo reduction processing is performed to produce the result. This design allows rapid redefinition of the degree and generator polynomial used for the ground field and the extension field.
    Type: Application
    Filed: October 22, 2001
    Publication date: July 17, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Sivagnanam Parthasarathy, Cinzia A. Bartolommei
  • Field effect transistor having dielectrically isolated sources and drains and method for making same
    Patent number: 6593174
    Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Redundancy circuit and method for replacing defective memory cells in a flash memory device
    Patent number: 6594177
    Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Stella Matarrese, Luca Giovanni Fasoli
  • Integrated volatile and non-volatile memory
    Patent number: 6594192
    Abstract: A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volatile memory. The volatile memory may be static or dynamic random access memory. The memory device may further include a control circuit connected to the at least one fuse to provide for prelaser testing.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: David C. McClure
  • On-chip automatic tuning technique
    Patent number: 6593802
    Abstract: A stable, process independent RC time constant for precision frequency response in automatic tuning is generated using a feedback loop employing a voltage controlled resistor to force current through the output node to equal a reference current. The only terms in the expression for the time constant affected by process variations are two resistances, which are uniformly affected by any process variations to maintain proportion. The open loop transfer function for the feedback loop contains only one pole; because no phase-locked loop or other complex circuit introducing multiple poles within the feedback loop are employed, the time constant tuning filter is intrinsically stable.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Giorgio Mariani, Valter Orlandini
  • System and method for dynamically controlling memory access prioritization
    Patent number: 6591350
    Abstract: A method and system are disclosed for dynamically changing the priority of memory requests to access a memory device in a disk drive system. In particular, the disk drive system includes a hard disk controller having a processing element for performing various operations and a buffer for providing an interface to a memory device, such as a random access memory. The buffer includes arbitration block to prioritize memory requests to access the memory device. A priority modification block is included to modify the assigned priorities so that the priority assigned to a pending memory request submitted by the processing element is increased. The priority modification block triggers the modification of priorities upon the occurrence of an event, such as the reception of an interrupt by the processing element or a memory request submitted by the processing element timing out.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: July 8, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: Ross John Stenfort
  • Random access memory cell and method for fabricating same
    Publication number: 20030122172
    Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Richard J. Ferrant, T. C. Chan
  • Apparatus for switching data in high-speed networks and method of operation
    Publication number: 20030123468
    Abstract: A packet switch for switching cells comprising fixed-size data packets.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Applicant: STMicroelectronics, Inc.
    Inventor: Ge Nong
  • System independent and scalable packet buffer management architecture for network processors
    Publication number: 20030123454
    Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.
    Type: Application
    Filed: November 8, 2002
    Publication date: July 3, 2003
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Faraydon O. Karim, Ramesh Chandra, Bernd H. Stramm
  • Self-timed digital processing circuits
    Publication number: 20030126172
    Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 3, 2003
    Applicant: STMICROELECTRONICS, INC.
    Inventor: William A. Chren
  • Scalable two-stage virtual output queuing switch and method of operation
    Publication number: 20030123469
    Abstract: A fixed-size data packet switch comprising: 1) N input ports for receiving incoming fixed-size data packets at a first data rate and outputting the fixed-size data packets at the first data rate; 2) N output ports for receiving fixed-size data packets at the first data rate and outputting the fixed-size data packets at the first data rate; and 3) a switch fabric interconnecting the N input ports and the N output ports.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Applicant: STMicroelectronics, Inc.
    Inventor: Ge Nong
  • Apparatus and method for transcoding still image data files into MPEG video data files and digital video player implementing same
    Publication number: 20030123857
    Abstract: The CPU breaks a digital still image file down into multiple sub-picture files. Each sub-picture file is treated as an MPEG video frame and is used to construct an MPEG video stream. An MPEG processor then processes the MPEG video stream. The MPEG processor decodes the video stream and scales each sub-picture down to fit a monitor or television upon which the still image is to be displayed. Each scaled sub-picture is stored in a display buffer but is not displayed until the entire MPEG video stream is decoded.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 3, 2003
    Applicant: STMicroelectronics, Inc.
    Inventors: Ren Egawa, Michael Robert Harris
  • Method and apparatus for improved transition from pulse width modulation to linear control
    Patent number: 6586896
    Abstract: A method and a circuit for switching a motor controller from pulse width modulation to linear control for a brush-less, sensor-less, poly-phase DC motor. The method includes steps of operating a drive circuit for a poly-phase direct current motor in a pulse width modulation mode and determining that a zero crossing will occur within a predetermined interval. The method also includes steps of enabling a bias current to a transconductance operational amplifier and changing an operating state of the drive circuit from the pulse width modulation mode to a linear mode. The method further includes steps of determining that the zero crossing has occurred, disabling the bias current to the transconductance operational amplifier and changing the operating state of the drive circuit from the linear mode to the pulse width modulation mode.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: Paolo Menegoli
  • Lead-frame forming for improved thermal performance
    Patent number: 6586821
    Abstract: A lead frame of a plastic integrated circuit package is fabricated in two steps. First, from a rectangular sheet of metal, lead fingers of the lead frame are formed. Second, the die pad of the lead frame is clamped and is simultaneously separated and downset from the lead fingers of the lead frame by shearing the lead frame with a mated punch die pair. Performing the separation and downset of the die pad from the lead fingers results in essentially no horizontal gap between the lead fingers and the die pad. The downset of the die pad with respect to the lead fingers results in a vertical separation between the die pad and the lead fingers.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Michael J. Hundt, Tiao Zhou
  • Driver circuit having a slew rate control system with improved linear ramp generator including ground
    Patent number: 6586980
    Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: Michael J. Callahan, Jr.
  • Code and method for encoding data
    Patent number: 6587059
    Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: July 1, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Francesco Rezzi, Marcus Marrow