Abstract: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. The processor detects one of the servo wedges on spin up of the disk, i.e., while the disk is attaining or after the disk attains an operating speed. By detecting a servo wedge instead of a spin-up wedge to determine an initial head position on disk spin up, such a servo circuit allows one to increase the disk's storage capacity by reducing the number of, or altogether eliminating, spin-up servo wedges from the disk.

Abstract: A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.

Abstract: A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the array of memory cells including row lines and column lines, each row line being coupled to memory cells in a distinct row of memory cells, each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes a redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon an address value received by the memory device during a memory access operation.

Abstract: A new synchronous Partial Response Maximum Likelihood (PRML) servo is provided for a high track-per-inch disk-drive system. To increase the data capacity in hard disk drives (HDD), one can shorten the servo format and/or increase the track density. The new servo system has circuits that allow a high-performance and accurate system for positioning the read-write heads. The major circuits include burst demodulation, Viterbi detection, timing synchronization, and spin-up search. A highly linear discrete-fourier-transform (DFT) burst-demodulation circuit can demodulate high-density and low-signal-to-noise-ratio (SNR) position bursts. The Viterbi detection circuit includes a sync-mark detector and a Viterbi detector that are matched to at least two sets of Gray code ( e.g., ¼ rate and {fraction (4/12)} rate) and pruned accordingly. The timing synchronization circuit includes phase restart and interpolating timing recovery (ITR) circuits to implement a fully digital timing recovery.

Abstract: A data-storage disk includes a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge indentifies the sector in conjunction with both an initial positioning of a read-write head and a data read or write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.

Abstract: A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: There is disclosed systems for multiplexing packetized elementary streams in a digital video recorder (DVR), methods of operating the same, and multiplexed program streams. One such system is associated with a DVR and operates to multiplex packetized elementary streams into a multiplexed program stream, the packetized elementary streams comprising PES packets of disparate size. The system is operable to (i) receive the PES packets into a memory buffer, (ii) reformat each of the received PES packets into at least one fixed-size program packet having a header and a payload, the header defining a payload content, and (iii) associate ones of the at least one fixed-size program packets into the multiplexed program stream.

Abstract: A method and device of creating one or more buffer structures in a shared memory that exists between a host and a network device is disclosed. The method includes the step of storing within a block of shared memory an administration block having a base address and a descriptor ring parameter, which includes information relating to a descriptor ring and frame data buffer sizes. The base address of the administration block is written into the network device. An initialization command is then issued from the host to the network device. The network device reads the administration block and shared memory and one or more descriptors are constructed within the network device. Each descriptor points to a frame data buffer within shared memory. The descriptors are then stored.

Abstract: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface uses information derived from the data packets received to form message control blocks, particular for each individual task, and places the control blocks into the proper task queue. The transaction interface forms a dispatcher message control block and places it into the scheduler/dispatcher queue to initiate the task. If there are no other message control blocks in the queue particular for the called task, the called task is immediately started.

Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 Å to 500 Å thick porous oxide over the device to protect the silicide from excessive exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract: A folded cascade voltage gain cell is implemented in a single stage by collapsing p-channel transistor branches receiving output currents from two sets of n-channel transistor branches and producing the output voltage into a single set of branches, summing the output currents from two sets of n-channel transistor branches in a single pair of nodes. While power consumption is only slightly improved over multistage folded cascade voltage gain cells, the circuit is implemented with fewer transistors and is therefore smaller and more reliable. Moreover, because only one gain stage is employed with a smaller number of internal nodes, the circuit's operation contains a smaller number of poles, and bandwidth is improved.

Abstract: An integrated circuit structure provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The test mode structure of the IC memory device has a number of bipolar transistors, a number of ETD transistors coupled to the bipolar transistors, and a logic element coupled to the bipolar and ETD transistors at a node. The ETD transistors operate to ensure that the emitter of corresponding bipolar transistors have a voltage of Vb−Vbe.

Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract: A new technique for Hard Disk Drive (HDD) servo-burst demodulation is provided. A 4-samples per dibit Discrete Fourier Transform (DFT) amplitude estimation is used to calculate the read-head servo-position error signal. Comparatively, the conventional method of burst demodulation—called burst integration—typically uses more than 8 samples/dibit. Consequently, the new 4-samples/dibit DFT burst-demodulation scheme requires fewer samples per dibit than does burst integration, thus reducing the disk space occupied by the burst data while increasing the performance as compared to burst integration. Furthermore, the DFT scheme does not require the samples to be synchronized to any particular points of the servo burst, and can include an averaging algorithm that further improves performance for a given Signal to Noise Ratio (SNR). Moreover, the same sample-clocking circuit that detects the Gray Code servo information can also implement the DFT burst-demodulation scheme to demodulate the servo burst.

Abstract: An LED driver circuit and method are disclosed where an array of light emitting diodes have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.

Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.