Abstract: The low temperature-corrected constant voltage generator device includes a reference voltage generator, an amplifier connected between the reference voltage generator and an output terminal and a voltage divider connected to an input of the amplifier in order to supply a feedback voltage to the amplifier. The divider includes at least one first resistor in series with an element having, at least in the low temperature range, an impedance with a temperature dependence behavior different from that of the first resistor, to supply a lower feedback in the low temperature range.

Abstract: An operational amplifier includes an input transconductor stage with differential inputs and an output, an output stage, and at least one intermediate stage connected between the input stage and the output stage so as to form an amplifier chain. The intermediate stage includes a common-emitter bipolar transistor between first and second power supply terminals, and at least one feedback resistor connected between the bipolar transistor emitter and one of the power supply terminals. The intermediate stage also includes at least one feedback capacitance connected between the emitter terminal of the transistor and an output of a next stage.

Abstract: A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.

Abstract: A circuit and method for reading a multiple-level floating-gate memory is provided. The reading is done by a gate bias voltage VP that is equal to the voltage needed to obtain a predetermined reference current Iref in the selected storage transistor. The decoding of the stored data element is done by the decoding of the bias voltage VP. Thus the circuit and method reduces the current flowing through the transistors during the reading and reduces the mean electrical stress undergone during each read operation.

Abstract: A circuit for the measurement of time intervals includes a generator providing primary periodic pulses, a frequency divider capable of transmitting secondary periodic pulses for scaling down the frequency of the primary periodic pulses, and a counter for counting the secondary periodic pulses transmitted during the measured time interval. The frequency divider is programmable by a digital factor which determines the frequency division. The circuit further includes a self-calibration circuit for modifying the digital factor as a function of the number of pulses counted by the counter during a previous time interval measurement.

Abstract: Process for producing electrical connections on the surface of a semiconductor package containing an integrated-circuit chip and having metal electrical-connection regions on the surface of the package, consisting of: covering these connection regions with a first metal layer forming an anti-diffusion barrier; covering this first layer with an anti-oxidation second metal layer; and depositing a metal solder drop or solder ball on the second metal layer. The solder drop comprises an addition of metal particles in suspension which contain at least one of the metals of the first metal layer so as to produce a precipitate comprising these additional metal particles and at least partly the metal of the second metal layer, the precipitate remaining in suspension in the solder drop.

Abstract: A method is provided for locally creating an aperture in a metal layer that is formed above a base wafer having at least one lateral mark provided in its peripheral edge and at least one surface mark provided at a point on its surface. Coordinates of a starting position of a tool with respect to the peripheral edge and the lateral mark are found, and coordinates of the position of the surface mark with respect to the starting position of the tool are calculated so as to determine a course to be followed by the tool from the starting position to a working position above the surface mark. The tool is moved to the working position and activated so as to etch the metal layer and create the aperture in the metal layer above the surface mark. Also provided is a device for locally creating an aperture in a metal layer that is formed above a base wafer.

Abstract: A self-powered peripheral apparatus is connected upstream to another apparatus via a universal serial bus (USB), wherein one of the conductors of the USB provides a supply voltage to the self-powered peripheral apparatus. One of the two data conductors of the USB is connected to a voltage source of the self-powered peripheral apparatus. The self-powered peripheral apparatus includes a control device for controlling the data conductor supply for supplying the latter only if the supply voltage is present on the supply conductor. The control device includes a circuit for detecting the supply voltage and a logic circuit for controlling the regulator.

Abstract: A process for adjusting a level of spurious signal spectral lines in an output frequency spectrum provided by a single-sideband frequency mixer includes the step of generating two mutually phase-shifted test signals defined by a plurality of parameters, and applying the two test signals to respective first and second inputs of the single-sideband frequency mixer. The level of each of the spurious signal spectral lines are measured for different test values corresponding to the plurality of parameters of the two test signals. Reference values are determined for the plurality of parameters for minimizing the level of the spurious signal spectral lines. The reference values are determined by a numerical calculation performed on a predetermined number of different test values of the plurality of parameters, and corresponding measured values of the levels with respect to two parabolic relations linking the levels of the two spurious signal spectral lines with the plurality of parameters.

Abstract: A device for protecting a structure of SOI type including several insulated cells, each cell being formed of a portion of a semiconductor substrate of a first conductivity type having its bottom and its lateral walls delimited by an insulating area. A protective cell includes a first semiconductor region of the second conductivity type connected to a reference potential and several second regions of the second conductivity type separated from one another and from the first region. The substrate portion of each of the cells other than the protective cell is connected to one of the second regions.

Abstract: Method of manufacturing a capacitor integrated onto a silicon substrate, comprising a step of depositing a layer of first electrode, a step of depositing a layer of a dielectric material, a step of exposure of the dielectric layer to a plasma and a step of depositing a layer of second electrode. This creates the advantage of a design of capacitors with metallic electrodes having a good linearity versus voltage.

Abstract: A method for communicating between a transmitting unit and a receiving unit. A message formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device and for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device.

Abstract: An interconnect level includes upper and lower partial levels having respective conductive lines offset heightwise from each other. The interconnect level further includes respective dielectric portions separating adjacent conductive lines and extends above and below the conductive lines. At least one descending via connects a conductive line of the upper partial level with a lower element located below the dielectric portions of the interconnect level. The at least one descending via extends through the dielectric portions separating adjacent conductive lines of the lower partial level. At least one ascending via connects a conductive line of the lower partial level with an upper element located above the dielectric portions of the interconnect level. At least one ascending via extends through the dielectric portions separating adjacent conductive lines of the upper partial level.

Abstract: A microprocessor circuit having an external memory interface includes a transmission element for the transmission of binary data packets between the microprocessor and the interface. The interface includes a buffer with a determined capacity for storing the transmitted data elements. The circuit also includes a controller capable of computing the capacity of the buffer that is available or unavailable owing to the storage of the data elements and capable of reporting the status of availability of the buffer to receive an additional packet. A method is also provided for the control of the interface of such a circuit. The interface comprises a decoder for decoding format data of a packet. The format data of a packet being contained in the data packet and each format data decoding operation being given to the controller in order to optimize the use of the storage capacity of the buffer and the transmission between the microprocessor and the external memory.

Abstract: In a reading device for a memory, a circuit for the asymmetrical precharging of the differential amplifier is provided so that an output of the reading device switches over to a determined state. In the following evaluation phase, if the memory cell is programmed, the output remains unchanged. If the memory cell is blank or erased, the output of the reading device switches over to another state. A detection circuit detects a sufficient difference between the inputs of the differential amplifier for stopping the asymmetrical precharging and for making the reading device go automatically to the evaluation phase.

Abstract: A device includes a capacitive structure including an input node and n output nodes, r integrated capacitors connected in series between two adjacent nodes, an integrated capacitor connected between the input node and ground, an integrated capacitor connected between the nth output node and ground, and r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch may include r+1 series-connected integrated capacitors. Furthermore, the integrated capacitors of the capacitive structure are theoretically identical. The device may also include a charge source for charging each node of the capacitive structure. Additionally, a measurement circuit may measure the charge at each of the nodes of the structure, and a comparison circuit may compare each measured nodal charge value with a theoretical nodal charge value while taking into account a predetermined nodal tolerance.

Abstract: A phase locked loop for a voltage controlled oscillator includes a phase comparator receiving at its inputs a reference frequency signal and a frequency signal from the oscillator, and supplies logic values to command a charge pump. A charge re-injection circuit receives one of the inputs of the comparator and supplies a logic value to command the charge pump. The loop further includes a detector with a threshold value for a current representative of the current supplied by the charge pump. A logic output from the detector is applied to the charge re-injection circuit so that the duration of the charge re-injection is limited.

Abstract: A process for color adjustment of a color monitor including a cathode-ray tube and a brightness adjustment module includes providing a nominal brightness signal downstream of a white level adjustment module for adjusting a white level and upstream of a black level adjustment module for adjusting a black level. The process also includes setting a voltage required to obtain a black color image, setting a voltage required to obtain a white color image, providing the nominal brightness signal upstream of the white level adjustment module, and setting the voltage required to obtain the black color image.

Abstract: A device is provided for calculating mutual phase shift of first and second incident signals. The device includes a first pair of blocks associated with the first incident signal, a second pair of blocks associated with the second incident signal, checking circuit, and post-processing circuit. Each of the blocks has storage elements for storing a predetermined set of samples of the corresponding incident signal. In the presence of minimum samples or maximum samples of both incident signals, the checking circuit stores a first set of samples relating to the first incident signal in one of the blocks of the first pair and a first set of samples relating to the second incident signal in the counterpart block of the second pair, and then stores the following sets of samples of each incident signal alternately in the two blocks of each pair. The checking circuit delivers a block validation signal when a set of samples has been completely stored in the storage elements of one of the blocks.

Abstract: A protection device includes a switching transistor (M11), connected between the gate of the output transistor (TS1) and ground, and a control circuit (CM), connected to the gate of the switching transistor (M11), which are capable of ensuring that the switching transistor (M11) is off when there is no electrostatic discharge at the drain of the output transistor (TS1) and capable of turning the switching transistor (M11) on when there is an electrostatic discharge at the drain of the output transistor (TS1).